final lec 1

final lec 1 - EECS 252 Graduate Computer Architecture Lec 8...

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EECS 252 Graduate Computer Architecture Lec 8 – Instruction Level Parallelism David Patterson Electrical Engineering and Computer Sciences University of California, Berkeley http://www.eecs.berkeley.edu/~pattrsn http://vlsi.cs.berkeley.edu/cs252-s06
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09/09/09 CS252 S06 Lec8 ILPB 2 Review from Last Time #1 Leverage Implicit Parallelism for Performance: Instruction Level Parallelism Loop unrolling by compiler to increase ILP Branch prediction to increase ILP Dynamic HW exploiting ILP Works when can’t know dependence at compile time Can hide L1 cache misses Code for one machine runs well on another
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09/09/09 CS252 S06 Lec8 ILPB 3 Review from Last Time #2 Reservations stations: renaming to larger set of registers + buffering source operands Prevents registers as bottleneck Avoids WAR, WAW hazards Allows loop unrolling in HW Not limited to basic blocks (integer units gets ahead, beyond branches) Helps cache misses as well Lasting Contributions Dynamic scheduling Register renaming Load/store disambiguation 360/91 descendants are Pentium 4, Power 5, AMD Athlon/Opteron, …
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09/09/09 CS252 S06 Lec8 ILPB 4 Outline ILP Speculation Speculative Tomasulo Example Memory Aliases Exceptions VLIW Increasing instruction bandwidth Register Renaming vs. Reorder Buffer Value Prediction Discussion about paper “Limits of ILP”
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09/09/09 CS252 S06 Lec8 ILPB 5 Speculation to greater ILP Greater ILP: Overcome control dependence by hardware speculating on outcome of branches and executing program as if guesses were correct Speculation fetch, issue, and execute instructions as if branch predictions were always correct Dynamic scheduling only fetches and issues instructions Essentially a data flow execution model : Operations execute as soon as their operands are available
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09/09/09 CS252 S06 Lec8 ILPB 6 Speculation to greater ILP 3 components of HW-based speculation: 1. Dynamic branch prediction to choose which instructions to execute 2. Speculation to allow execution of instructions before control dependences are resolved + ability to undo effects of incorrectly speculated sequence 1. Dynamic scheduling to deal with scheduling of different combinations of basic blocks
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09/09/09 CS252 S06 Lec8 ILPB 7 Adding Speculation to Tomasulo Must separate execution from allowing instruction to finish or “commit” This additional step called instruction commit When an instruction is no longer speculative, allow it to update the register file or memory Requires additional set of buffers to hold results of instructions that have finished execution but have not committed This reorder buffer ( ROB ) is also used to pass results among instructions that may be speculated
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09/09/09 CS252 S06 Lec8 ILPB 8 Reorder Buffer (ROB) In Tomasulo’s algorithm, once an instruction writes its result, any subsequently issued instructions will find result in the register file With speculation, the register file is not updated
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This note was uploaded on 08/30/2009 for the course CSE 420 taught by Professor Skousen,a during the Spring '08 term at ASU.

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final lec 1 - EECS 252 Graduate Computer Architecture Lec 8...

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