lab1 - ECE 3150 Lab 1 MOS TRANSISTORS MEASURING...

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ECE 3150 Lab 1 9/9/2009 MOS T RANSISTORS : M EASURING T HREE -T ERMINAL D EVICES 1 Objectives In this lab, you will learn the basic operating regions of NMOSFET and PMOSFET transistors, and learn how to use the simple source and measuring unit (SMU) to obtain their electrical characteristics. You will also learn the data acquisition procedure using MATLAB. 2 Prelab 2.1 Description of NMOSFET and PMOSFET in CMOS The following prelab questions have been constructed to help you prepare to do the lab efficiently. These questions are folded into homework. Please review them again before you come to lab. Solutions will be posted before the lab. To function as a switch, transistors must have at least three terminals: one for input, one for output and one for the common reference potential. There are at least two voltages needed to define the operating point of the transistor, and it is of utmost importance that you learn this setup of two voltages by heart in this lab so that you will not be further confused into the semester. By definition, an NMOSFET has heavily-doped n-type source and drain regions and the current is always carried by electrons. The physical transistor structure is usually symmetric 1 , and in an NMOS 2 , the terminal with the higher potential is called the “drain”, and the lower potential the “source”. In CMOS design, the source of the NMOS is often grounded (if possible). Usually NMOS has a p-type channel region, and can be turned on (or called “strong inversion to form an n-channel”) with a positive gate bias voltage with respect to the grounded source terminal. This gives NMOS a positive small-signal transconductance , i.e., the output current increases when the control voltage increases. If we sweep the gate bias V GS with a constant V DS (remember V DS in an NMOS is always positive, by definition), we will get appreciable amount of the drain current I D when V GS > V th , the threshold voltage. The dependence of I D on V GS is illustrated in Fig. 1 in both linear and log scales. Another way to look at V th is: When V GS < V th , I D is small and decreases exponentially with decreasing V GS . When V GS > V th , I D is large and only increases linearly or quadratically with increasing V GS . We will now look at the dependence of I D on V DS , i.e., the output characteristics. If V GS > V th (“ above threshold ”), when V DS is larger than a saturation voltage V Dsat , which can often be approximated with V GS – V th = V OV the overdrive gate bias, the NMOS is said to be in saturation , with I D almost independent of V DS . If V DS < V Dsat , the NMOS is in the linear or triode region, with I D linearly or quadratically dependent on V DS (the name of triode means that I D is now sensitive to both V GS and V DS , as all three electrodes are influencing I D ). There is another important point for V Dsat . When V GS < V th (“ subthreshold ”), a small (positive) V DS should already drive the NMOS into saturation. In reality, V Dsat in subthreshold is not zero but at 3 to 5 times of V T = kT/q . However, there is still some small but non-
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