book06 - Power-Aware Resource Management Techniques for...

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Unformatted text preview: Power-Aware Resource Management Techniques for Low-Power Embedded Systems Jihong Kim School of Computer Science & Engineering Seoul National University Seoul, Korea 151-742 E-mail: [email protected] Tajana Simunic Rosing Department of Computer Science & Engineering University of California, San Diego La Jolla, CA 92093, USA E-mail: [email protected] July 2, 2006 1 1 INTRODUCTION 2 1 Introduction Energy consumption has become one of the most important design constraints for modern embedded systems, especially for mobile embedded systems that operate with a limited energy source such as batteries. For these systems, the design process is characterized by a tradeoff between a need for high performance and low power consumption, emphasizing high performance to meeting the performance constraints while minimizing the power consumption. Decreasing the power consumption not only helps with extending the battery lifetime in portable devices, but is also a critical factor in lowering the packaging and the cooling costs of embedded systems. While better low-power circuit design techniques have helped to lower the power consumption [9, 41, 34], managing power dissipation at higher abstraction levels can considerably decrease energy requirements [14, 3]. Since we will be focusing on dynamic power P dynamic in this chapter, the total power dissipation P CMOS can be approximated as P CMOS ≈ P dynamic . The dynamic power of CMOS circuits is dissipated when the output capacitance is charged or discharged, and is given by P dynamic = α · C L · V 2 dd · f clk where α is the switching activity (the average number of high-to-low transitions per cycle), C L is the load capacitance, V dd is the supply voltage, and f clk is the clock frequency. The energy consumption during the time interval [0 ,T ] is given by E = integraltext T P ( t ) dt ∝ V 2 dd · f clk · T = V 2 dd · N cycle where P ( t ) is the power dissipation at t and N cycle is the number of clock cycles during the interval [0 ,T ]. These equations indicate that a significant energy saving can be achieved by reducing the supply voltage V dd ; a decrease in the supply voltage by a factor of two yields a decrease in the energy consumption by a factor of four. In this chapter, we focus on the system-level power-aware resource management techniques. System-level power management technqiues can be roughly classified into two categories, dynamic voltage scaling (DVS) and dynamic power management (DPM). Dynamic voltage scaling (DVS) [7], which can be applied in both hardware and software desgin abstractions, is one of most effective design techniques in minimizing the energy consumption of VLSI systems. Since the energy consumption E of CMOS circuits has a quadratic dependency on the supply voltage, lowering the supply voltage reduces the energy consumption significantly....
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This note was uploaded on 09/01/2009 for the course CSE CS-699 taught by Professor Prf.p.bhaduri during the Spring '09 term at Indian Institute of Technology, Guwahati.

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book06 - Power-Aware Resource Management Techniques for...

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