power aware 22 - Scheduling Techniques to Enable Power...

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Scheduling Techniques to Enable Power Management Jos´e Monteiro, Srinivas Devadas Pranav Ashar Ashutosh Mauskar Department of EECS, MIT Synopsys, Inc. Cambridge, MA Princeton, NJ Mountain View, CA “Shut-down” techniques are effective in reducing the power dissipation of logic circuits. Recently, methods have been devel- oped that identify conditions under which the output of a module in a logic circuit is not used for a given clock cycle. When these conditions are met, input latches for that module are disabled, thus eliminating any switching activity and power dissipation. In this paper, we introduce these power management techniques in behavioral synthesis. We present a scheduling algorithm which maximizes the “shut-down” period of execution units in a sys- tem. Given a throughput constraint and the number of execution units available, the algorithm first schedules operations that gen- erate controlling signals and activates only those modules whose result is eventually used. We present results which show that this scheduling technique can save up to 40% in power dissipation. I. INTRODUCTION Rapid increases in chip complexity, increasingly faster clocks, and the proliferation of portable devices have combined to make power dissipation an important design parameter. The power dissipated by a digital system determines its heat dissipation as well as battery life. Power reduction techniques have been proposed at all levels – from system to device. It has been demonstrated at the gate and system levels that large power savings are possible merely by cutting down on wasted power – commonly referred to as power management. At the system level, this involves shutting down blocks of hardware that are not being used ([3], Chapter 10). Detection and shut down of unused hardware is done automatically in current generations of Pentium and PowerPC processors. The Fujitsu SPARClite processor provides software con- trols for shutting down hardware. It has been shown in recent work that similar power management techniques are effective at the sequential [1] and combinational logic [6], [9] levels also. Application of power management at the gate level involves first identifying large portions of the circuit that fre- quently produce information that is either not essential for determin- ing the values on the primary outputs, or information that could have been produced by much simpler hardware. Additional hardware is then added to the circuit that detects on a per-clock-cycle basis in- put conditions under which such a situation arises and shuts down the corresponding portions of the circuit for that clock cycle. The goal of our work is to introduce power management into scheduling algorithms used in behavioral level synthesis. Behavioral synthesis comprises of the sequence of steps by means of which an algorithmic specification is translated into hardware. These steps in- volve breaking down the algorithm into primitive operations, and as-
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power aware 22 - Scheduling Techniques to Enable Power...

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