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power aware 23 - Scheduling and resource binding for low...

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Scheduling and resource binding for low power E. Musoll and J. Cortadella Department of Computer Architecture Universitat Polit`ecnica de Catalunya 08071-Barcelona, Spain Abstract Decisions taken at the earliest steps of the design pro- cess may have a significant impact on the characteristics of the final implementation. This paper illustrates how power consumption issues can be tackled during the scheduling and resource-binding steps of high-level synthesis. Algo- rithms for these steps targeting at low-power data-paths and trading off, in some cases, speed and area for low power are presented. The algorithms focus on reducingthe activity of the func- tional units (adders, multipliers) by minimizing the transi- tions of their input operands. The power consumption of the functional units accounts for a large fraction of the overall data-path power budget. 1 Introduction Current VLSI technology allows circuits with more and more functionalityto be integrated in just one chip. Nowa- days, portable applications are not only wrist clocks or calculators but multi-media terminals, mobile telephones and other real-time systems. These new applications are based on intensive data-path tasks such as video compres- sion, speech recognition and other digital signal processing tasks. The portable feature of these applications imposes a limit on power consumption whereas the real-time char- acteristic forces the designer to comply with the required throughput. Power consumption can be taken into account at differ- ent levels in the design process [4]: technological, topo- logical, architectural and algorithmic levels. High-level synthesis (HLS) comprises techniques at the architectural and algorithmic level. Design decisions taken in the HLS process have a significant impact on the quality of the fi- nal implementation. Traditionally, HLS has been applied to obtain small and fast designs, but including power con- sumption as one of the design parameters or constraints has rarely been addressed. Preliminary studies in the HLS steps of scheduling and resource binding[9] targeting at low power reported in [14] have guided the algorithms presented in this paper. The main target for reducing power consumption is the set of functional units (adders, multipliers) because its power consumption accounts for a large fraction of the overall data-path power budget. The algorithms attempt to reduce the activity of the functional units by minimizing the switching activity of their input operands. Models derived from switch-level simulations of the main data-path components (functional, interconnection and storage units) [14] will be used to estimate the power reduction achieved with the algorithms. The paper is organized as follows: in Section 2, pre- vious work on low-power circuits with special insight in high-level techniques is briefly presented. Section 3 dis- cusses how thefunctional unitsconsume power in data-path intensive systems. It briefly describes the scheduling and resource-binding tasks along with the basic ideas behind the algorithms presented in the paper. Sections 4 and 5 de-
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