hardware accelerated power estimation

hardware accelerated power estimation - Hardware...

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Hardware Accelerated Power Estimation Joel Coburn, Srivaths Ravi, and Anand Raghunathan NEC Laboratories America, 4 Independence Way, Princeton, NJ 08540 jcoburn,sravi,anand @nec-labs.com Abstract In this paper, we present power emulation , a novel design paradigm that utilizes hardware acceleration for the purpose of fast power esti- mation. Power emulation is based on the observation that the functions necessary for power estimation (power model evaluation, aggregation, etc. ) can be implemented as hardware circuits. Therefore, we can en- hance any given design with “power estimation hardware”, map it to a prototyping platform, and exercise it with any given test stimuli to obtain power consumption estimates. Our empirical studies with industrial de- signs reveal that power emulation can achieve significant speedups (10X to 500X) over state-of-the-art commercial register-transfer level (RTL) power estimation tools. 1 INTRODUCTION Power estimation is an important part of the design process for most in- tegrated circuits. The problem of power estimation has been researched at varying levels of abstraction, and many of the resulting techniques have been incorporated into commercial power estimation tools. How- ever, efficient power estimation for large designs remains a challenge due to increases in design and testbench complexity. For example, RTL power estimation for a 1.25 million transistor MPEG4 decoder circuit (for an input stimulus containing 4 frames of a video stream) required 43 minutes and 55 minutes to run on two different state-of-the-art com- mercial tools [1, 2]. Power estimation tools that operate at the transistor and gate levels are known to be much (10X to 100X) slower. To achieve efficient power estimation, we harness the speedup of hardware acceleration that comes from using an emulation platform. Typically, power estimation is dominated by the evaluation of compo- nent power models based on circuit inputs during simulation. The key observation of this work is that power model functionality can be im- plemented as hardware circuits. In practice, we can augment any design with power estimation hardware and map it to a hardware emulation platform such as an FPGA. To the best of our knowledge, this is the first effort to leverage hardware acceleration for the purpose of power esti- mation. We apply the concept of power emulation to power estimation at the register-transfer level, and present a design flow incorporating this idea. We demonstrate the benefits of power emulation by reporting the speedups in power estimation time for several large designs. The results indicate that power emulation can significantly enhance the scope of current RTL and gate-level power estimation methods by making them applicable to large designs with little or no tradeoff in accuracy. Much like functional emulation, we believe that power emulation will provide designers with the ability to study the power consumption of a design under realistic environments and operating conditions.
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This note was uploaded on 09/01/2009 for the course CSE CS-699 taught by Professor Prf.p.bhaduri during the Spring '09 term at Indian Institute of Technology, Guwahati.

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hardware accelerated power estimation - Hardware...

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