cacti - FEBRUARY 2000 WRL Research Report 2000/7 CACTI 2.0:...

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F E B R U A R Y 2 0 0 0 WRL Research Report 2000/7 CACTI 2.0: An Integrated Cache Timing and Power Model Glen Reinman and Norman P. Jouppi Western Research Laboratory 250 University Avenue Palo Alto, California 94301 USA
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The Western Research Laboratory (WRL), located in Palo Alto, California, is part of Compaq’s Corporate Research group. WRL was founded by Digital Equipment Corpora- tion in 1982. We focus on information technology that is relevant to the technical strategy of the Corporation, and that has the potential to open new business opportunities. Research at WRL includes Internet protocol design and implementation, tools to optimize compiled binary code files, hardware and software mechanisms to support scalable shared memory, graphics VLSI ICs, handheld computing, and more. As part of WRL tradition, we test our ideas by extensive software or hardware prototyping. We publish the results of our work in a variety of journals, conferences, research reports, and technical notes. This document is a research report. Research reports are normally accounts of completed research and may include material from earlier technical notes, conference papers, or magazine articles. We use technical notes for rapid distribu- tion of technical material; usually this represents research in progress. You can retrieve research reports and technical notes via the World Wide Web at: http://www.research.compaq.com/wrl/ You can request printed copies of research reports and technical notes, when available, by mailing your order to us at: Technical Report Distribution Compaq Western Research Laboratory 250 University Avenue Palo Alto, California 94301 U.S.A. You can also request reports and notes by sending e-mail to: WRL-techreports@research.compaq.com
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CACTI 2.0: An Integrated Cache Timing and Power Model Glen Reinman and Norman P. Jouppi Compaq Computer Corporation Western Research Laboratory reinman@cs.ucla.edu, norm.jouppi@compaq.com February, 2000 Copyright 2000, 2002, Compaq Computer Corporation Western Research Laboratory 250 University Avenue Palo Alto, California 94301 USA Abstract CACTI 2.0 is an integrated cache access time, cycle time, and power model. By integrat- ing all these models together users can have confidence that tradeoffs between time and power are all based on the same assumptions and hence are mutually consistent. CACTI is intended for use by computer architects so they can better understand the performance tradeoffs inherent in different cache sizes and organizations. This report details enhancements to CACTI 1.0 that are included in CACTI 2.0. CACTI 2.0 includes modeling support for fully-associative caches, a cache power model, technology scaling, multiported caches, improved tag comparison circuits, and other improvements to CACTI 1.0.
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An Integrated Cache Timing and Power Model Glenn Reinman Norm Jouppi Summer Internship 1999 COMPAQ Western Research Lab, Palo Alto 1 CACTI CACTI [6] calculates access and cycle times of hardware caches. It uses an analytical model to estimate delay
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This note was uploaded on 09/01/2009 for the course CSE CS-699 taught by Professor Prf.p.bhaduri during the Spring '09 term at Indian Institute of Technology, Guwahati.

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cacti - FEBRUARY 2000 WRL Research Report 2000/7 CACTI 2.0:...

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