e3 - The Time-Triggered Architecture HERMANN KOPETZ FELLOW...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
The Time-Triggered Architecture HERMANN KOPETZ, FELLOW, IEEE AND GÜNTHER BAUER Invited Paper The time-triggered architecture (TTA) provides a computing in- frastructure for the design and implementation of dependable dis- tributed embedded systems. A large real-time application is decom- posed into nearly autonomous clusters and nodes, and a fault-tol- erant global time base of known precision is generated at every node. In the TTA, this global time is used to precisely specify the interfaces among the nodes, to simplify the communication and agreement protocols, to perform prompt error detection, and to guarantee the timeliness of real-time applications. The TTA sup- ports a two-phased design methodology, architecture design, and component design. During the architecture design phase, the in- teractions among the distributed components and the interfaces of the components are fully specified in the value domain and in the temporal domain. In the succeeding component implementation phase, the components are built, taking these interface specifica- tions as constraints. This two-phased design methodology is a pre- requisite for the composability of applications implemented in the TTA and for the reuse of prevalidated components within the TTA. This paper presents the architecture model of the TTA, explains the design rationale, discusses the time-triggered communication pro- tocols TTP/C and TTP/A, and illustrates how transparent fault tol- erance can be implemented in the TTA. Keywords— Distributed systems, embedded systems, real-time systems, safety-critical systems, time-triggered architecture (TTA), TTP/C. I. INTRODUCTION Computer architectures establish a blueprint and a frame- work for the design of a class of computing systems that share a common set of characteristics. The time-triggered architecture (TTA) generates such a framework for the domain of large distributed embedded real-time systems in high-dependability environments. It sets up the computing Manuscript received December 20, 2001; revised August 31, 2002. This work was supported in part by the European Information Society Technolo- gies projects NEXT TTA, Fault Injection for Time-Triggered Architectures, Systems Engineering for Time-Triggered Architectures, and Dependable Systems of Systems; in part by the Time-Triggered Sensor Bus project of the government of Austria; and in part by the Defense Advanced Research Projects Agency projects Model-Based Integration of Embedded Software and Networked Embedded Software Technology. The authors are with the Vienna University of Technology, A-1040 Vi- enna, Austria (e-mail:[email protected]; [email protected]). Digital Object Identifier 10.1109/JPROC.2002.805821 infrastructure for the implementation of applications and provides mechanisms and guidelines to partition a large application into nearly autonomous subsystems along small and well-defined interfaces in order to control the complexity of the evolving artifact [1]. Architecture design
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 2
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 09/01/2009 for the course CSE CS-699 taught by Professor Prf.p.bhaduri during the Spring '09 term at Indian Institute of Technology, Guwahati.

Page1 / 15

e3 - The Time-Triggered Architecture HERMANN KOPETZ FELLOW...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online