e4 - Voltage Reduction Techniques for Portable Systems...

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Voltage Reduction Techniques for Portable Systems Anan tha Chandrakasan Department of EECS, Massachusetts Institute of Technology, Cambridge ABSTRACT Supply voltage scaling to 1V and below is the key to low-power system design. Threshold voltage reduction enables aggressive supply scaling but increases leakage power. Emerging technologies such as MTCMOS and variable threshold Bulk/SOI will be essential in controlling leakage while achieving high performance levels at low supply voltages. Power can also be reduced by adap- tively varying the supply voltage in applications where the computational workload varies with time. Aggressive volt- age and power level-scaling requires efficient DC-DC conversion circuitry and in some cases, it is necessary to embed this function in the processor. 1. Introduction There are three main sources of power consumption in digital CMOS circuits: switching power, short circuit power, and leakage power. In conventional process tech- nology, the switching component dominates and is given by a.CL. VDD .AVfClkwhere a is the node transition activ- ity factor, CL is load capacitance, VD~ is the supply volt- age, AV is the voltage swing, and fclk is the clock frequency. A variety of techniques have been proposed to reduce switching activity ranging from low level logic restructuring and power down techniques, to architectural restructuring and selection of data representation [I]. It is important to consider transitions that are fundamentally required to perform a given operation as well as spurious transitions arising from imbalances in the signal path. The most efficient approach to lower energy con- sumption is to operate at the lowest possible power sup- ply voltage. The individual circuit elements, however, run slower at lower supply voltages and circuit performance degrades. One approach to maintain throughput at reduced voltages is to use parallel architectures to com- pensate for increased gate delays [l]. Significant power reduction over conventional approaches is possible at the cost of increased silicon area. A variety of voltage scaling strategies are described here which reduce power without significantly increasing silicon area. Associated with aggressive voltage and power scaling is the need for high-efficiency regulation techniques. In many cases, embedding the power converter control in the processor can significantly reduce power dissipation. 1063-0988/97/$10.00 0 1997 IEEE. The short circuit component of power can be kept to less than 10% of the total power through proper transistor sizing. The third component is the leakage power, result- ing from reverse biased diode conduction and subthresh- old operation. Scaling supply voltages below 1 V requires the scaling of the threshold voltage, which unfortunately comes at the cost of increased leakage. While leakage is typically negligible when circuits are active, it can be sig- nificant during idle mode. A variety of technology and cir- cuit solutions are discussed here which address the
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This note was uploaded on 09/01/2009 for the course CSE CS-699 taught by Professor Prf.p.bhaduri during the Spring '09 term at Indian Institute of Technology, Guwahati.

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e4 - Voltage Reduction Techniques for Portable Systems...

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