e1 - IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION...

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Unformatted text preview: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 5, NO. 4, DECEMBER 1997 425 Embedded Power Supply for Low-Power DSP Vadim Gutnik and Anantha P. Chandrakasan, Member, IEEE Abstract— The use of dynamically adjustable power supplies as a method to lower power dissipation in DSP is analyzed. Power can be reduced substantially without sacrificing performance in fixed-throughput applications by slowing the clock and lowering supply voltage instead of idling when computational workload varies. This can yield a typical power savings of 30–50%. If latency can be tolerated, buffering data and averaging processing rate can yield power reductions of an order of magnitude in some applications. Continuous variation of the supply voltage can be approximated by very crude quantization and dithering: a four- level controller is sufficient to get within a few percent of the optimal power savings. Significant savings are possible only if the voltage can be changed on the same time scale as the variations in workload. A chip has been fabricated and tested to verify the closed-loop functionality of a variable voltage system. The controller takes only 0.4 mm 2 and draws a maximum of 1 mW at 2 V with a 40 MHz clock. The control framework developed is applicable to generic DSP applications. Index Terms— Low-power DSP, variable supply voltage, work- load averaging. I. INTRODUCTION A. Motivation M OST techniques to lower power consumption of in- tegrated circuits (IC’s) assume static behavior; that is, circuit and system parameters are chosen at design time to minimize power dissipation. In fact, in some applications adjusting the circuit during operation could save more power. The number of operations performed per sample in many digital signal processor (DSP) systems can be minimized dy- namically by exploiting time-varying signal statistics. MPEG video is one such example. Since frames of video are highly correlated to each other, most digital processing begins by comparing consecutive frames and processing only the differ- ences. The amount of computation necessary to process the differences depends on how much the image changes from frame to frame. Typically, each frame is divided into small blocks and only those that change more than a threshold are processed. Thus, the amount of computation per frame in an MPEG encoder varies dramatically between a scene change (the entire frame encoded) and most other incrementally different frames. A more generic application is described in [1]: the number of taps of an FIR filter is varied based on the power of the out-of-band noise. The idea is to keep just enough taps in the FIR such that the stopband energy in the Manuscript received September 8, 1996; revised May 15, 1997. This work was supported by DARPA under Contract DAAL01-95-K-3526. V. Gutnik was supported by an NDSEG Fellowship....
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This note was uploaded on 09/01/2009 for the course CSE CS-699 taught by Professor Prf.p.bhaduri during the Spring '09 term at Indian Institute of Technology, Guwahati.

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e1 - IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION...

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