Lecture33-MOS+Logic+Gate+Design

Lecture33-MOS+Logic+Gate+Design - ECE 3040: Microelectronic...

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ECE 3040 - Dr. Ying Zhang Georgia Tech ECE 3040: Microelectronic Circuits Lecture 33 Reading: Jaeger 6.1-6.12, Notes
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ECE 3040 - Dr. Ying Zhang Georgia Tech ± Resistive Load Inverter ± Load Line Visualization ± Noise Margin Analysis ± NMOS Saturated Load Inverter Agenda
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ECE 3040 - Dr. Ying Zhang Georgia Tech C L “Pull Up” Resistor provides current to Charge up the Load Capacitor, C L Load Capacitor, C L , represents the total capacitance of all gates that would be connected to the output (Input capacitance's of the MOSFETS) Switching transistor will “Pull down” the output voltage by discharging the Load Capacitor, C l when the transistor is conducting. Note: V BS =0 Resistive Load Inverter
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ECE 3040 - Dr. Ying Zhang Georgia Tech C L Resistive Load Inverter R i V v v D DD DS o = = For v i =v GS =V OL <V T OH DD o D V V v i = = = 0 V OL <V T is our first design criteria! For a nominal V T = 1, we would typically make V OL ~0.25V to insure adequate noise margin.
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ECE 3040 - Dr. Ying Zhang Georgia Tech C L Resistive Load Inverter R i V v v D DD DS o = = For v i =v GS =V OH =V DD from previous page, v o =V OL ! region linear the in be must we V v and v V v Since OL O DS DD GS = > =
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ECE 3040 - Dr. Ying Zhang Georgia Tech Resistive Load Inverter The MOSFET switches between the two operating points, v GS <V T (cutoff) and v GS =V DD (Linear) along a “Resistive” (linear IV characteristic) “Load Line” passing through the saturation region during the transition. v GS <V T (cutoff) v GS =V DD (Linear)
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ECE 3040 - Dr. Ying Zhang Georgia Tech Resistive Load Inverter Example: If we wanted the gate to dissipate 0.25 mW using a V TN =1V and K n ’=25e-6 A/V
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This note was uploaded on 09/05/2009 for the course ECE 3040 taught by Professor Hamblen during the Spring '07 term at Georgia Institute of Technology.

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Lecture33-MOS+Logic+Gate+Design - ECE 3040: Microelectronic...

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