lecture7-pre

# lecture7-pre - BME 303 Lecture 7 Just Finished...

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1 1 BME 303 Lecture 7 • Just Finished: Combinational Logic Circuits • Sequential Logic Circuits – R-S Latches (Flip-flops) – Gated D-Latches – Registers • Memory • Finite State Machines 2 • HW #2 due today – turn it in now! • Solutions to HW #1 and #2 posted ASAP • HW #3 due next Tuesday, February 15 • Looking ahead: Exam #1 in 2 weeks (HW #4 due date may be moved up because of exam – Feb 18?) • Engineering Computer Account: If you don’t already have one, get one: https://utdirect.utexas.edu/engine/adrequest.WBX • Questions 3 Problem Language Machine (ISA) Architecture Algorithms Micro-architecture Circuits Devices Data Path Finite State Machines Memory Storage Elements R-S Latch Gated D latch Register Logic Structures Decoder Mux (multiplexer) Adder Logic Gates NOT OR AND Other gates Transistors Devices, Circuits, … Bottom Up 4 Combinational vs. Sequential Combinational Circuit – always gives the same output for a given set of inputs – Example: adder always generates sum and carry, regardless of previous inputs Sequential Circuit – stores information – output depends on stored information ( state ) plus input • A given input might produce different outputs, depending on the stored information – Example: ticket counter • advances when you push the button • output depends on previous state – useful for building “ memory ” elements and “ finite state machines 5 Combinational Success depends only on the values , not the order in which they are set. Sequential Success depends on the sequence of values (Right 35, Left 5, Right 17) 6 R-S Latch: Simple Storage Element • R is used to “reset” or “clear” the element – set it to zero. • S is used to “set” the element – set it to one. • If both R and S are one, “out” could be either zero or one. – “quiescent” state – holds its previous value – Note: b = ~a 1 0 1 1 1 1 0 0 1 1 0 0 1 1

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2 7 Clearing the R-S latch • Suppose we start with output = 1, then change R to zero. Output changes to zero. Then set R = 1 to “store” value in quiescent state. 1 0 1 1 1 1 0 0 1 0 1 0 0 0 1 1 8 Setting the R-S Latch • Suppose we start with output = 0, then change S to zero. Output changes to one. 1 1 0 0 1 1 0 1 1 1 0 0 Then set S = 1 to “store” value in quiescent state. 9 R-S Latch Summary R = S = 1 – Hold current value in latch S = 0, R = 1 – Set value to 1 R = 0, S = 1 – Set value to 0 R = S = 0 – Both outputs equal one – Final state determined by detailed electrical properties of gates Error! (Don’t do it!) 10 R-S Latch (004_RS_Latch.lgi) 11 Gated D-Latch • Two inputs: D (data) and WE (write enable) – when WE = 1 , latch is set to value of D • S = NOT(D), R = D – when WE = 0 , latch holds previous value • S = R = 1 12 Gated D Latch (005_D_Latch.lgi)
3 13 Register • A register stores a multi-bit value.

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## This note was uploaded on 09/06/2009 for the course BME 303 taught by Professor Ren during the Spring '08 term at University of Texas.

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lecture7-pre - BME 303 Lecture 7 Just Finished...

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