systemverilog_3.1_final

systemverilog_3.1_final - SystemVerilog 3.1 Accellera's...

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SystemVerilog 3.1 Accellera’s Extensions to Verilog ® Abstract: a set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language to aid in the creation and verification of abstract architectural level models
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Copyright © 2002, 2003 by Accellera Organization, Inc. 1370 Trancas Street #163 Napa, CA 94558 Phone: (707) 251-9977 Fax: (707) 251-9877 All rights reserved. No part of this document may be reproduced or distributed in any medium what- soever to any third parties without prior written consent of Accellera Organization, Inc. SystemVerilog 3.1 Accellera’s Extensions to Verilog ® Abstract: a set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language to aid in the creation and verification of abstract architectural level models
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Accellera SystemVerilog 3.1 Extensions to Verilog-2001 ii Copyright 2003 Accellera. All rights reserved. Verilog is a registered trademark of Cadence Design Systems, San Jose, CA
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Accellera Extensions to Verilog-2001 SystemVerilog 3.1 Copyright 2003 Accellera. All rights reserved. iii Acknowledgements This SystemVerilog Language Reference Manual was developed by experts from many different fields, includ- ing design and verification engineers, Electronic Design Automation (EDA) companies, EDA vendors, and members of the IEEE 1364 Verilog standard working group. The SystemVerilog Language Reference Manual (LRM) was specified by the Accellera SystemVerilog com- mittee. Four subcommittees worked on various aspects of the SystemVerilog 3.1 specification: The Basic Committee (SV-BC) worked on errata and clarification of the SystemVerilog 3.0 LRM. The Enhancement Committee (SV-EC) investigated and specified new modeling and testbench features. The Assertions Committee (SV-AC) specified the assertions constructs for SystemVerilog 3.1. The C Application Programming Interface (API) Committee (SV-CC) developed and specified the Direct Programming Interface (DPI), the assertions API and the coverage API for SystemVerilog. The committee chairs were: Vassilios Gerousis, SystemVerilog 3.0 and 3.1 Committee General Chair Dave Kelf, SystemVerilog 3.0 Committee Co-Chair Johny Srouji, SystemVerilog 3.1 Basic Committee Chair; Karen Pieper, Co-Chair David Smith, SystemVerilog 3.1 Enhancement Committee Chair; Stefen Boyd, Co-Chair Faisal Haque, SystemVerilog 3.1 Assertions Committee Chair; Steve Meier, Co-Chair Swapnajit Mittra, SystemVerilog 3.1 C API Committee Chair; Ghassan Khoory, Co-Chair Stuart Sutherland, SystemVerilog 3.0 and 3.1 Language Reference Manual Editor Stefen Boyd, SystemVerilog 3.0 and 3.1 BNF Annex. Editor Committee members included (listed alphabetically by last name): * indicates this person was also an active member of the IEEE 1364 Verilog Standard Working Group. SystemVerilog 3.0 Committee SystemVerilog 3.1 Basic Committee SystemVerilog 3.1 Enhancement Committee SystemVerilog 3.1 Assertions Committee SystemVerilog 3.1 C API Committee Stefen Boyd* Dennis Brophy Kevin Cameron Cliff Cummings* Simon Davidmann Tom Fitzpatrick* Peter Flake Harry Foster Vassilios Gerousis Paul Graham Dave Kelf David Knapp* Adam Krolnik* Mike McNamara* Phil Moorby
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