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Unformatted text preview: SIS: A System for Sequential Circuit Synthesis Electronics Research Laboratory Memorandum No. UCB/ERL M92/41 Ellen M. Sentovich Kanwar Jit Singh Luciano Lavagno Cho Moon Rajeev Murgai Alexander Saldanha Hamid Savoj Paul R. Stephan Robert K. Brayton Alberto Sangiovanni-Vincentelli Department of Electrical Engineering and Computer Science University of California, Berkeley, CA 94720 4 May 1992 Abstract SIS is an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table, a signal transition graph, or a logic-level description of a sequential circuit, it produces an optimized net-list in the target technologywhile preserving the sequential input-output behavior. Many different programs and algorithms have been integrated into SIS, allowing the user to choose among a variety of techniques at each stage of the process. It is built on top of MISII  and includes all (combinational) optimization techniques therein as well as many enhancements. SIS serves as both a framework within which various algorithms can be tested and compared, and as a tool for automatic synthesis and optimization of sequential circuits. This paper provides an overview of SIS. The first part contains descriptions of the input specification, STG (state transition graph) manipulation, new logic optimization and verification algorithms, ASTG (asynchronous signal transition graph) manipulation, and synthesis for PGAs (programmable gate arrays). The second part contains a tutorial example illustrating the design process using SIS. 1 Introduction The SIS synthesis system is specifically targeted for sequential circuits and supports a design methodology that allows the designer to search a larger solution space than was previously possible. In current practice the synthesis of sequential circuits proceeds much like synthesis of combinational circuits: sequential circuits are divided into purely combinational blocks and registers. Combinational optimization techniques are applied to the combinational logic blocks, which are later reconnected to the registers to form a single circuit. This limits the optimization by fixing the register positions and optimizing logic only within combinational blocks without exploiting signal dependencies across register boundaries. Verification techniques are limited to verifying machines with the same encoding. Finally, it is cumbersome to separate the circuit into logic and registers only to reconstruct it later. In this paper, a sequential circuit design methodology is described; it is implemented through a system that employs state-of-the-art synthesis and optimization techniques. This approach is illustrated with an example demonstrating the usefulness of these new techniques and the flexibility the designer can exploit during the synthesis process....
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