sis_lab_tutorial_2_logic_synthesis

sis_lab_tutorial_2_logic_synthesis - 7HFKQRORJ\ PDSSLQJ...

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Unformatted text preview: 7HFKQRORJ\ PDSSLQJ XVLQJ 6,6 Laboratory 2 in course Logic synthesis 2002-version Written by Tomas Bengtsson and Shashi Kumar /RJLF RSWLPLVDWLRQ XVLQJ 6,6 7RPDV %HQJWVVRQ 7RPDV %HQJWVVRQ#LQJ KM VH 6KDVKL .XPDU 6KDVKL .XPDU#LQJ KM VH- 2 - ,QWURGXFWLRQ BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 'RFXPHQWV QHHGHG IRU WKLV ODEBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 5HFRPPHQGHG SUHSDUDWLRQV IRU WKLV ODE BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 6KRUW LQWURGXFWLRQ WR )3*$V BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB ,QIRUPDWLRQ DERXW &/%V XVHG LQ WKLV ODE BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 7DVNV BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 0DNLQJ VFULSWV IRU WHFKQRORJ\ PDSSLQJ BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 7HFKQRORJ\ PDSSLQJ RI PXOWLSOLHUBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 7HFKQRORJ\ PDSSLQJ RI *UD\ FRGH FRQYHUWHU BBBBBBBBBBBBBBBBBBBBBBBBBBB 7HFKQRORJ\ PDSSLQJ RI D EHQFKPDUNBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB $Q H[DPSOH RI 7HFKQRORJ\ PDSSLQJBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 'HVFULSWLRQ RI H[DPSOH BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 6RPH WLSVBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 7KH H[DPSOH WKURXJK 6,6 BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB 7.3.1. Gate Decomposition _____________________________________________9 7.3.2. LUT Mapping _________________________________________________11 7.3.3. Post-processing commands _______________________________________12 7.3.4. Programmable Logic Block Generation _____________________________14 /RJLF RSWLPLVDWLRQ XVLQJ 6,6 7RPDV %HQJWVVRQ 7RPDV %HQJWVVRQ#LQJ KM VH 6KDVKL .XPDU 6KDVKL .XPDU#LQJ KM VH- 3 - ,QWURGXFWLRQ After a circuit has been optimized using Logic Optimization tools, the next step is to bring the circuit closer to implementation by using the available information about implementation technology. This step is called Technology Mapping. This step involves converting the abstract description (FSM or Boolean functions) of the circuit to a network of limited type of components, normally from a library of components. Due to this reason, Technology Mapping is also sometimes referred as Library Binding. This step involves, selecting components from the library and forming a network of these components. Normally the objectives in Technology Mapping are to have the final implementation using a minimum number of components or to minimize the area of the implementation. Technology mapping to an FPGA results in the final implementation suitable for a specific FPGA type from a specific company. This is because the internal architecture of FPGAs from different companies is quite different. The internal architectures of various FPGAs from the same company also differ depending on the component series. For example, XILINX 4000 series FPGA has different type of logic blocks as compared to 3000 series. There are two further steps after a circuit has been converted to a network of blocks of a FPGA. These steps are called 3ODFHPHQW...
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This note was uploaded on 09/09/2009 for the course EECS 318 taught by Professor Saab during the Fall '01 term at Case Western.

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sis_lab_tutorial_2_logic_synthesis - 7HFKQRORJ\ PDSSLQJ...

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