report - M.A College of Engineering FFT Processor 1 M.A...

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Unformatted text preview: M.A. College of Engineering FFT Processor 1 M.A. College of Engineering FFT Processor 2 TABLE OF CONTENTS LIST OF FIGURES…………………………………………………… Chapter 1-Introduction to VHDL 1 . 1 I n t r o d u c t i o n 1 1.2 Advantages of VHDL over other Hardware… Description Languages……………………………………….. 1 1.3 VHDL : The Language…………………………………… 2 1.3.1 Entity Declaration……………………………….. 3 1.3.2 Architecture Body……………………………….. 3 1.3.3 Configuration Declaration……………………….. 7 1.3.4 Package…………………………………………… 8 1.3.5 Testbench………………………………………… 9 Chapter 2-High Level Design Flow…………………………………. 10 2.1 HDL Capture……………………………………………… 10 2.2 RTL Simulation…………………………………………… 10 2.3 VHDL Synthesis………………………………………….. 12 2.4 Functional Gate Level Verification………………………. 13 2.5 Place and Route…………………………………………... 1 3 2.6 Post Layout Timing Simulation………………………….. 15 Chapter 3-Illustration of VHDL…………………………………….. 16 3.1 The IEEE floating-point standard………………………… 16 3.2 The Addition Process…………………………………….. 17 3.3 Hardware Implementation of Floating-Point Adder……… 19 3.3.1 Block Diagram of the Adder…………………….. 19 3.3.2 The Subtractor Unit……………………………… 20 3.3.3 The Swap Unit…………………………………… 21 3.3.4 The Shifter Unit………………………………….. 22 3.3.5 The Summer Unit………………………………… 23 3.3.6 The Normalize Unit………………………………. 23 3.3.7 The Control Unit…………………………………. 24 3.3.8 The Testbench for the adder……………………… 28 Chapter 4- The Fourier Transform…………………………………… 30 4.1 The Discrete Fourier Transform…………………………... 30 4.1.1 An Illustration…………………………………….. 30 4.1.2 Types of Fourier Transforms……………………... 31 4.1.3 Notation and Format of the Real DFT……………. 33 4.1.4 DFT Basis Functions……………………………… 34 4.1.5 Analysis, Calculating the DFT……………………. 37 4.2 The Fast Fourier Transform………………………………. 37 4.2.1 Comparison of Real DFT and Complex DFT……. 38 4.2.2 How the FFT works……………………………… 39 4.3 Synthesis, Calculating the Inverse DFT………………….. 42 4.4 Illustration of the DFT and IDFT in Matlab……………… 44 Chapter 5-Architectural Design of the FFT Processor……………… 46 5.1 Block Diagram of the FFT Processor…………………….. 46 M.A. College of Engineering M....
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report - M.A College of Engineering FFT Processor 1 M.A...

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