p1076_chap_01 - LANGUAGE REFERENCE MANUAL IEEE Std...

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LANGUAGE REFERENCE MANUAL IEEE Std P 1076a -1999 2000/D3 Section Clause 1 5 Copyright © 2000, IEEE. All rights reserved. This is an unapproved IEEE Standards Draft, subject to change. Section Clause 1 1 Design entities and configurations The design entity is the primary hardware abstraction in VHDL. It represents a portion of a hardware design that has well-defined inputs and outputs and performs a well-defined function. A design entity may represent an entire system, a subsystem, a board, a chip, a macro-cell, a logic gate, or any level of abstraction in between. A config- uration can be used to describe how design entities are put together to form a complete design. A design entity may be described in terms of a hierarchy of blocks , each of which represents a portion of the whole design. The top-level block in such a hierarchy is the design entity itself; such a block is an external block that resides in a library and may be used as a component of other designs. Nested blocks in the hierarchy are internal blocks, defined by block statements (see 9.1). A design entity may also be described in terms of interconnected components. Each component of a design entity may be bound to a lower-level design entity in order to define the structure or behavior of that component. Suc- cessive decomposition of a design entity into components, and binding those components to other design entities that may be decomposed in like manner, results in a hierarchy of design entities representing a complete design. Such a collection of design entities is called a design hierarchy . The bindings necessary to identify a design hi- erarchy can be specified in a configuration of the top-level entity in the hierarchy. This section clause 2 describes the way in which design entities and configurations are defined. A design entity is defined by an entity declaration together with a corresponding architecture body . A configuration is defined by a configuration declaration . 1.1 Entity declarations An entity declaration defines the interface between a given design entity and the environment in which it is used. It may also specify declarations and statements that are part of the design entity. A given entity declaration may be shared by many design entities, each of which has a different architecture. Thus, an entity declaration can po- tentially represent a class of design entities, each with the same interface. entity_declaration ::= entity identifier is entity_header entity_declarative_part [ begin entity_statement_part ] end [ entity ] [ entity _simple_name ] ; The entity header and entity declarative part consist of declarative items that pertain to each design entity whose interface is defined by the entity declaration. The entity statement part, if present, consists of concurrent state- ments that are present in each such design entity.
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  • Fall '01
  • Saab
  • United States Declaration of Independence, IEEE Standards Association, Design Entity, IEEE Standards Draft, IEEE Std P1076a-1999 2000/D3

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