p1076_app_a - LANGUAGE REFERENCE MANUAL IEEE Std...

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Unformatted text preview: LANGUAGE REFERENCE MANUAL IEEE Std P1076a-1999 2000/D3 Annex A Syntax summary (informative) This annex provides a summary of the syntax for VHDL. Productions are ordered alphabetically by left-hand nonterminal name. The clause number indicates the clause where the production is given. abstract_literal ::= decimal_literal | based_literal access_type_definition ::= access subtype_indication actual_designator ::= expression | signal_name | variable_name | file_name | open actual_parameter_part ::= parameter_association_list actual_part ::= actual_designator | function_name ( actual_designator ) | type_mark ( actual_designator ) adding_operator ::= + | | & aggregate ::= ( element_association { , element_association } ) alias_declaration ::= alias alias_designator [ : subtype_indication ] is name [ signature ] ; alias_designator ::= identifier | character_literal | operator_symbol allocator ::= new subtype_indication | new qualified_expression [ 13.4] [ 3.3] [ 4.3.2.2] [ 7.3.3] [ 4.3.2.2] [ 7.2] [ 7.3.2] [ 4.3.3] [ 4.3.3] [ 7.3.6] Annex A Copyright 2000, IEEE. All rights reserved. This is an unapproved IEEE Standards Draft, subject to change. 219 IEEE Std P1076a-1999 2000/D3 IEEE STANDARD VHDL architecture_body ::= architecture identifier of entity_name is architecture_declarative_part begin architecture_statement_part end [ architecture ] [ architecture_simple_name ] ; architecture_declarative_part ::= { block_declarative_item } architecture_statement_part ::= { concurrent_statement } array_type_definition ::= unconstrained_array_definition | constrained_array_definition assertion ::= assert condition [ report expression ] [ severity expression ] assertion_statement ::= [ label : ] assertion ; association_element ::= [ formal_part => ] actual_part association_list ::= association_element { , association_element } attribute_declaration ::= attribute identifier : type_mark ; attribute_designator ::= attribute_simple_name attribute_name ::= prefix [ signature ] ' attribute_designator [ ( expression ) ] attribute_specification ::= attribute attribute_designator of entity_specification is expression ; base ::= integer base_specifier ::= B | O | X base_unit_declaration ::= identifier ; based_integer ::= extended_digit { [ underline ] extended_digit } based_literal ::= base # based_integer [ . based_integer ] # [ exponent ] basic_character ::= basic_graphic_character | format_effector [ 1.2] [ 1.2.1] [ 1.2.2] [ 3.2.1] [ 8.2] [ 8.2] [ 4.3.2.2] [ 4.3.2.2] [ 4.4] [ 6.6] [ 6.6] [ 5.1] [ 13.4.2] [ 13.7] [ 3.1.3]1 [ 13.4.2] [ 13.4.2] [ 13.1] 1. The LHS of this production was renamed to "primary_unit_declaration" in 1076-1993. 220 Copyright 2000, IEEE. All rights reserved. This is an unapproved IEEE Standards Draft, subject to change. Annex A LANGUAGE REFERENCE MANUAL IEEE Std P1076a-1999 2000/D3 basic_graphic_character ::= upper_case_letter | digit | special_character| space_character basic_identifier ::= letter { [ underline ] letter_or_digit } binding_indication ::= [ use entity_aspect ] [ generic_map_aspect ] [ port_map_aspect ] bit_string_literal ::= base_specifier " [ bit_value ] " bit_value ::= extended_digit { [ underline ] extended_digit } block_configuration ::= for block_specification { use_clause } { configuration_item } end for ; block_declarative_item ::= subprogram_declaration | subprogram_body | type_declaration | subtype_declaration | constant_declaration | signal_declaration | shared_variable_declaration | file_declaration | alias_declaration | component_declaration | attribute_declaration | attribute_specification | configuration_specification | disconnection_specification | use_clause | group_template_declaration | group_declaration block_declarative_part ::= { block_declarative_item } block_header ::= [ generic_clause [ generic_map_aspect ; ] ] [ port_clause [ port_map_aspect ; ] ] block_specification ::= architecture_name | block_statement_label | generate_statement_label [ ( index_specification ) ] [ 13.1] [ 13.3.1] [ 5.2.1] [ 13.7] [ 13.7] [ 1.3.1] [ 1.2.1] [ 9.1] [ 9.1] [ 1.3.1] Annex A Copyright 2000, IEEE. All rights reserved. This is an unapproved IEEE Standards Draft, subject to change. 221 IEEE Std P1076a-1999 2000/D3 IEEE STANDARD VHDL block_statement ::= block_label : block [ ( guard_expression ) ] [ is ] block_header block_declarative_part begin block_statement_part end block [ block_label ] ; block_statement_part ::= { concurrent_statement } case_statement ::= [ case_label : ] case expression is case_statement_alternative { case_statement_alternative } end case [ case_label ] ; case_statement_alternative ::= when choices => sequence_of_statements character_literal ::= ' graphic_character ' choice ::= simple_expression | discrete_range | element_simple_name | others choices ::= choice { | choice } component_configuration ::= for component_specification [ binding_indication ; ] [ block_configuration ] end for ; component_declaration ::= component identifier [ is ] [ local_generic_clause ] [ local_port_clause ] end component [ component_simple_name ] ; component_instantiation_statement ::= instantiation_label : instantiated_unit [ generic_map_aspect ] [ port_map_aspect ] ; component_specification ::= instantiation_list : component_name composite_type_definition ::= array_type_definition | record_type_definition [ 9.1] [ 9.1] [ 8.8] [ 8.8] [ 13.5] [ 7.3.2] [ 7.3.2] [ 1.3.2] [ 4.5] [ 9.6] [ 5.2] [ 3.2] 222 Copyright 2000, IEEE. All rights reserved. This is an unapproved IEEE Standards Draft, subject to change. Annex A LANGUAGE REFERENCE MANUAL IEEE Std P1076a-1999 2000/D3 concurrent_assertion_statement ::= [ label : ] [ postponed ] assertion ; concurrent_procedure_call_statement ::= [ label : ] [ postponed ] procedure_call ; concurrent_signal_assignment_statement ::= [ label : ] [ postponed ] conditional_signal_assignment | [ label : ] [ postponed ] selected_signal_assignment concurrent_statement ::= block_statement | process_statement | concurrent_procedure_call_statement | concurrent_assertion_statement | concurrent_signal_assignment_statement | component_instantiation_statement | generate_statement condition ::= boolean_expression condition_clause ::= until condition conditional_signal_assignment ::= target <= options conditional_waveforms ; conditional_waveforms ::= { waveform when condition else } waveform [ when condition ] configuration_declaration ::= configuration identifier of entity_name is configuration_declarative_part block_configuration end [ configuration ] [ configuration_simple_name ] ; configuration_declarative_item ::= use_clause | attribute_specification | group_declaration configuration_declarative_part ::= { configuration_declarative_item } configuration_item ::= block_configuration | component_configuration configuration_specification ::= for component_specification binding_indication ; constant_declaration ::= constant identifier_list : subtype_indication [ := expression ] ; constrained_array_definition ::= array index_constraint of element_subtype_indication [ 9.4] [ 9.3] [ 9.5] [ 9] [ 8.1] [ 8.1] [ 9.5.1] [ 9.5.1] [ 1.3] [ 1.3] [ 1.3] [ 1.3.1] [ 5.2] [ 4.3.1.1] [ 3.2.1] Annex A Copyright 2000, IEEE. All rights reserved. This is an unapproved IEEE Standards Draft, subject to change. 223 IEEE Std P1076a-1999 2000/D3 IEEE STANDARD VHDL constraint ::= range_constraint | index_constraint context_clause ::= { context_item } context_item ::= library_clause | use_clause decimal_literal ::= integer [ . integer ] [ exponent ] declaration ::= type_declaration | subtype_declaration | object_declaration | interface_declaration | alias_declaration | attribute_declaration | component_declaration | group_template_declaration | group_declaration | entity_declaration | configuration_declaration | subprogram_declaration | package_declaration delay_mechanism ::= transport | [ reject time_expression ] inertial design_file ::= design_unit { design_unit } design_unit ::= context_clause library_unit designator ::= identifier | operator_symbol direction ::= to | downto disconnection_specification ::= disconnect guarded_signal_specification after time_expression ; discrete_range ::= discrete_subtype_indication | range element_association ::= [ choices => ] expression element_declaration ::= identifier_list : element_subtype_definition ; element_subtype_definition ::= subtype_indication entity_aspect ::= entity entity_name [ ( architecture_identifier) ] | configuration configuration_name | open [ 4.2] [ 11.3] [ 11.3] [ 13.4.1] [ 4] [ 8.4] [ 11.1] [ 11.1] [ 2.1] [ 3.1] [ 5.3] [ 3.2.1] [ 7.3.2] [ 3.2.2] [ 3.2.2] [ 5.2.1.1] 224 Copyright 2000, IEEE. All rights reserved. This is an unapproved IEEE Standards Draft, subject to change. Annex A LANGUAGE REFERENCE MANUAL IEEE Std P1076a-1999 2000/D3 entity_class ::= entity | procedure | type | signal | label | group [ 5.1] | architecture | function | subtype | variable | literal | file | configuration | package | constant | component | units [ 4.6] [ 4.6] [ 1.1] entity_class_entry ::= entity_class [ <> ] entity_class_entry_list ::= entity_class_entry { , entity_class_entry } entity_declaration ::= entity identifier is entity_header entity_declarative_part [ begin entity_statement_part ] end [ entity ] [ entity_simple_name ] ; entity_declarative_item ::= subprogram_declaration | subprogram_body | type_declaration | subtype_declaration | constant_declaration | signal_declaration | shared_variable_declaration | file_declaration | alias_declaration | attribute_declaration | attribute_specification | disconnection_specification | use_clause | group_template_declaration | group_declaration entity_declarative_part ::= { entity_declarative_item } entity_designator ::= entity_tag [ signature ] entity_header ::= [ formal_generic_clause ] [ formal_port_clause ] entity_name_list ::= entity_designator { , entity_designator } | others | all entity_specification ::= entity_name_list : entity_class [ 1.1.2] [ 1.1.2] [ 5.1] [ 1.1.1] [ 5.1] [ 5.1] Annex A Copyright 2000, IEEE. All rights reserved. This is an unapproved IEEE Standards Draft, subject to change. 225 IEEE Std P1076a-1999 2000/D3 IEEE STANDARD VHDL entity_statement ::= concurrent_assertion_statement | passive_concurrent_procedure_call_statement | passive_process_statement entity_statement_part ::= { entity_statement } entity_tag ::= simple_name | character_literal | operator_symbol enumeration_literal ::= identifier | character_literal enumeration_type_definition ::= ( enumeration_literal { , enumeration_literal } ) exit_statement ::= [ label : ] exit [ loop_label ] [ when condition ] ; exponent ::= E [ + ] integer | E integer expression ::= relation { and relation } | relation { or relation } | relation { xor relation } | relation [ nand relation ] | relation [ nor relation ] | relation { xnor relation } extended_digit ::= digit | letter extended_identifier ::= \ graphic_character { graphic_character } \ factor ::= primary [ ** primary ] | abs primary | not primary file_declaration ::= file identifier_list : subtype_indication [ file_open_information ] ; file_logical_name ::= string_expression file_open_information ::= [ open file_open_kind_expression ] is file_logical_name file_type_definition ::= file of type_mark floating_type_definition ::= range_constraint formal_designator ::= generic_name | port_name | parameter_name formal_parameter_list ::= parameter_interface_list [ 1.1.3] [ 1.1.3] [ 5.1] [ 3.1.1] [ 3.1.1] [ 8.11] [ 13.4.1] [ 7.1] [ 13.4.2] [ 13.3.2] [ 7.1] [ 4.3.1.4] [ 4.3.1.4] [ 4.3.1.4] [ 3.4] [ 3.1.4] [ 4.3.2.2] [ 2.1.1] 226 Copyright 2000, IEEE. All rights reserved. This is an unapproved IEEE Standards Draft, subject to change. Annex A LANGUAGE REFERENCE MANUAL IEEE Std P1076a-1999 2000/D3 formal_part ::= formal_designator | function_name ( formal_designator ) | type_mark ( formal_designator ) full_type_declaration ::= type identifier is type_definition ; function_call ::= function_name [ ( actual_parameter_part ) ] generate_statement ::= generate_label : generation_scheme generate [ { block_declarative_item } begin ] { concurrent_statement } end generate [ generate_label ] ; generation_scheme ::= for generate_parameter_specification | if condition generic_clause ::= generic ( generic_list ) ; generic_list ::= generic_interface_list generic_map_aspect ::= generic map ( generic_association_list ) graphic_character ::= basic_graphic_character | lower_case_letter | other_special_character group_constituent ::= name | character_literal group_constituent_list ::= group_constituent { , group_constituent } group_declaration ::= group identifier : group_template_name ( group_constituent_list ) ; group_template_declaration ::= group identifier is ( entity_class_entry_list ) ; guarded_signal_specification ::= guarded_signal_list : type_mark identifier ::= basic_identifier | extended_identifier identifier_list ::= identifier { , identifier } [ 4.3.2.2] [ 4.1] [ 7.3.3] [ 9.7] [ 9.7] [ 1.1.1] [ 1.1.1.1] [ 5.2.1.2] [ 13.1] [ 4.7] [ 4.7] [ 4.7] [ 4.6] [ 5.3] [ 13.3] [ 3.2.2] Annex A Copyright 2000, IEEE. All rights reserved. This is an unapproved IEEE Standards Draft, subject to change. 227 IEEE Std P1076a-1999 2000/D3 IEEE STANDARD VHDL if_statement ::= [ if_label : ] if condition then sequence_of_statements { elsif condition then sequence_of_statements } [ else sequence_of_statements ] end if [ if_label ] ; incomplete_type_declaration ::= type identifier ; index_constraint ::= ( discrete_range { , discrete_range } ) index_specification ::= discrete_range | static_expression index_subtype_definition ::= type_mark range <> indexed_name ::= prefix ( expression { , expression } ) instantiated_unit ::= [ component ] component_name | entity entity_name [ ( architecture_identifier ) ] | configuration configuration_name instantiation_list ::= instantiation_label { , instantiation_label } | others | all integer ::= digit { [ underline ] digit } integer_type_definition ::= range_constraint interface_constant_declaration ::= [ constant ] identifier_list : [ in ] subtype_indication [ := static_expression ] interface_declaration ::= interface_constant_declaration | interface_signal_declaration | interface_variable_declaration | interface_file_declaration interface_element ::= interface_declaration interface_file_declaration ::= file identifier_list : subtype_indication interface_list ::= interface_element { ; interface_element } interface_signal_declaration ::= [signal] identifier_list : [ mode ] subtype_indication [ bus ] [ := static_expression ] [ 8.7] [ 3.3.1] [ 3.2.1] [ 1.3.1] [ 3.2.1] [ 6.4] [ 9.6] [ 5.2] [ 13.4.1] [ 3.1.2] [ 4.3.2] [ 4.3.2] [ 4.3.2.1] [ 4.3.2] [ 4.3.2.1] [ 4.3.2] 228 Copyright 2000, IEEE. All rights reserved. This is an unapproved IEEE Standards Draft, subject to change. Annex A LANGUAGE REFERENCE MANUAL IEEE Std P1076a-1999 2000/D3 interface_variable_declaration ::= [variable] identifier_list : [ mode ] subtype_indication [ := static_expression ] iteration_scheme ::= while condition | for loop_parameter_specification label ::= identifier letter ::= upper_case_letter | lower_case_letter letter_or_digit ::= letter | digit library_clause ::= library logical_name_list ; library_unit ::= primary_unit | secondary_unit literal ::= numeric_literal | enumeration_literal | string_literal | bit_string_literal | null logical_name ::= identifier logical_name_list ::= logical_name { , logical_name } logical_operator ::= and | or | nand | nor | xor | xnor loop_statement ::= [ loop_label : ] [ iteration_scheme ] loop sequence_of_statements end loop [ loop_label ] ; miscellaneous_operator ::= ** | abs | not mode ::= in | out | inout | buffer | linkage multiplying_operator ::= * | / | mod | rem name ::= simple_name | operator_symbol | selected_name | indexed_name | slice_name | attribute_name next_statement ::= [ label : ] next [ loop_label ] [ when condition ] ; null_statement ::= [ label : ] null ; [ 4.3.2] [ 8.9] [ 9.7] [ 13.3.1] [ 13.3.1] [ 11.2] [ 11.1] [ 7.3.1] [ 11.2] [ 11.2] [ 7.2] [ 8.9] [ 7.2] [ 4.3.2] [ 7.2] [ 6.1] [ 8.10] [ 8.13] Annex A Copyright 2000, IEEE. All rights reserved. This is an unapproved IEEE Standards Draft, subject to change. 229 IEEE Std P1076a-1999 2000/D3 IEEE STANDARD VHDL numeric_literal ::= abstract_literal | physical_literal object_declaration ::= constant_declaration | signal_declaration | variable_declaration | file_declaration operator_symbol ::= string_literal options ::= [ guarded ] [ delay_mechanism ] package_body ::= package body package_simple_name is package_body_declarative_part end [ package body ] [ package_simple_name ] ; package_body_declarative_item ::= subprogram_declaration | subprogram_body | type_declaration | subtype_declaration | constant_declaration | shared_variable_declaration | file_declaration | alias_declaration | use_clause | group_template_declaration | group_declaration package_body_declarative_part ::= { package_body_declarative_item } package_declaration ::= package identifier is package_declarative_part end [ package ] [ package_simple_name ] ; package_declarative_item ::= subprogram_declaration | type_declaration | subtype_declaration | constant_declaration | signal_declaration | shared_variable_declaration | file_declaration | alias_declaration | component_declaration | attribute_declaration | attribute_specification | disconnection_specification | use_clause | group_template_declaration | group_declaration [ 7.3.1] [ 4.3.1] [ 2.1] [ 9.5] [ 2.6] [ 2.6] [ 2.6] [ 2.5] [ 2.5] 230 Copyright 2000, IEEE. All rights reserved. This is an unapproved IEEE Standards Draft, subject to change. Annex A LANGUAGE REFERENCE MANUAL IEEE Std P1076a-1999 2000/D3 package_declarative_part ::= { package_declarative_item } parameter_specification ::= identifier in discrete_range physical_literal ::= [ abstract_literal ] unit_name physical_type_definition ::= range_constraint units base_unit_declaration { secondary_unit_declaration } end units [ physical_type_simple_name ] port_clause ::= port ( port_list ) ; port_list ::= port_interface_list port_map_aspect ::= port map ( port_association_list ) prefix ::= name | function_call primary ::= name | literal | aggregate | function_call | qualified_expression | type_conversion | allocator | ( expression ) primary_unit ::= entity_declaration | configuration_declaration | package_declaration primary_unit_declaration ::= identifier ; procedure_call ::= procedure_name [ ( actual_parameter_part ) ] procedure_call_statement ::= [ label : ] procedure_call ; [ 2.5] [ 8.9] [ 3.1.3] [ 3.1.3] [ 1.1.1] [ 1.1.1.2] [ 5.2.1.2] [ 6.1] [ 7.1] [ 11.1] [ 3.1.3]2 [ 8.6] [ 8.6] 2. The LHS of this production was renamed from "base_unit_declaration" in 1076-1993. Annex A Copyright 2000, IEEE. All rights reserved. This is an unapproved IEEE Standards Draft, subject to change. 231 IEEE Std P1076a-1999 2000/D3 IEEE STANDARD VHDL process_declarative_item ::= subprogram_declaration | subprogram_body | type_declaration | subtype_declaration | constant_declaration | variable_declaration | file_declaration | alias_declaration | attribute_declaration | attribute_specification | use_clause | group_template_declaration | group_declaration process_declarative_part ::= { process_declarative_item } process_statement ::= [ process_label : ] [ postponed ] process [ ( sensitivity_list ) ] [ is ] process_declarative_part begin process_statement_part end [ postponed ] process [ process_label ] ; process_statement_part ::= { sequential_statement } protected_type_body ::= protected body protected_type_body_declarative_part end protected body [ protected_type_simple name ] protected_type_body_declarative_item ::= subprogram_declaration | subprogram_body | type_declaration | subtype_declaration | constant_declaration | variable_declaration | file_declaration | alias_declaration | attribute_declaration | attribute_specification | use_clause | group_template_declaration | group_declaration protected_type_body_declarative_part ::= { protected_type_body_declarative_item } protected_type_declaration ::= protected protected_type_declarative_part end protected [ protected_type_simple_name ] [ 9.2 ] [ 9.2 ] [ 9.2 ] [ 9.2 ] [ 3.5.2] [ 3.5.2] [ 3.5.2] [ 3.5.1] 232 Copyright 2000, IEEE. All rights reserved. This is an unapproved IEEE Standards Draft, subject to change. Annex A LANGUAGE REFERENCE MANUAL IEEE Std P1076a-1999 2000/D3 protected_type_declarative_item ::= subprogram_declaration | attribute_specification | use_clause protected_type_declarative_part ::= { protected_type_declarative_item } protected_type_definition ::= protected_type_declaration | protected_type_body qualified_expression ::= type_mark ' ( expression ) | type_mark ' aggregate range ::= range_attribute_name | simple_expression direction simple_expression range_constraint ::= range range record_type_definition ::= record element_declaration { element_declaration } end record [ record_type_simple_name ] relation ::= shift_expression [ relational_operator shift_expression ] relational_operator ::= = | /= | < | <= | > | >= report_statement ::= [ label : ] report expression [ severity expression ] ; return_statement ::= [ label : ] return [ expression ] ; scalar_type_definition ::= enumeration_type_definition | integer_type_definition | floating_type_definition | physical_type_definition secondary_unit ::= architecture_body | package_body secondary_unit_declaration ::= identifier = physical_literal ; selected_name ::= prefix . suffix selected_signal_assignment ::= with expression select target <= options selected_waveforms ; [ 3.5.1] [ 3.5.1] [ 3.5] [ 7.3.4] [ 3.1] [ 3.1] [ 3.2.2] [ 7.1] [ 7.2] [ 8.3] [ 8.12] [ 3.1] [ 11.1] [ 3.1.3] [ 6.3] [ 9.5.2] Annex A Copyright 2000, IEEE. All rights reserved. This is an unapproved IEEE Standards Draft, subject to change. 233 IEEE Std P1076a-1999 2000/D3 IEEE STANDARD VHDL selected_waveforms ::= { waveform when choices , } waveform when choices sensitivity_clause ::= on sensitivity_list sensitivity_list ::= signal_name { , signal_name } sequence_of_statements ::= { sequential_statement } sequential_statement ::= wait_statement | assertion_statement | report_statement | signal_assignment_statement | variable_assignment_statement | procedure_call_statement | if_statement | case_statement | loop_statement | next_statement | exit_statement | return_statement | null_statement shift_expression ::= simple_expression [ shift_operator simple_expression ] shift_operator ::= sll | srl | sla | sra | rol | ror sign ::= + | signal_assignment_statement ::= [ label : ] target <= [ delay_mechanism ] waveform ; signal_declaration ::= signal identifier_list : subtype_indication [ signal_kind ] [ := expression ] ; signal_kind ::= register | bus signal_list ::= signal_name { , signal_name } | others | all signature ::= [ [ type_mark { , type_mark } ] [ return type_mark ] ] simple_expression ::= [ sign ] term { adding_operator term } simple_name ::= identifier slice_name ::= prefix ( discrete_range ) string_literal ::= " { graphic_character } " [ 9.5.2] [ 8.1] [ 8.1] [ 8] [ 8] [ 7.1] [ 7.2] [ 7.2] [ 8.4] [ 4.3.1.2] [ 4.3.1.2] [ 5.3] [ 2.3.2] [ 7.1] [ 6.2] [ 6.5] [ 13.6] 234 Copyright 2000, IEEE. All rights reserved. This is an unapproved IEEE Standards Draft, subject to change. Annex A LANGUAGE REFERENCE MANUAL IEEE Std P1076a-1999 2000/D3 subprogram_body ::= subprogram_specification is subprogram_declarative_part begin subprogram_statement_part end [ subprogram_kind ] [ designator ] ; subprogram_declaration ::= subprogram_specification ; subprogram_declarative_item ::= subprogram_declaration | subprogram_body | type_declaration | subtype_declaration | constant_declaration | variable_declaration | file_declaration | alias_declaration | attribute_declaration | attribute_specification | use_clause | group_template_declaration | group_declaration subprogram_declarative_part ::= { subprogram_declarative_item } subprogram_kind ::= procedure | function subprogram_specification ::= procedure designator [ ( formal_parameter_list ) ] | [ pure | impure ] function designator [ ( formal_parameter_list ) ] return type_mark subprogram_statement_part ::= { sequential_statement } subtype_declaration ::= subtype identifier is subtype_indication ; subtype_indication ::= [ resolution_function_name ] type_mark [ constraint ] suffix ::= simple_name | character_literal | operator_symbol | all target ::= name | aggregate term ::= factor { multiplying_operator factor } [ 2.2] [ 2.1] [ 2.2] [ 2.2] [ 2.2] [ 2.1] [ 2.2] [ 4.2] [ 4.2] [ 6.3] [ 8.4] [ 7.1] Annex A Copyright 2000, IEEE. All rights reserved. This is an unapproved IEEE Standards Draft, subject to change. 235 IEEE Std P1076a-1999 2000/D3 IEEE STANDARD VHDL timeout_clause ::= for time_expression type_conversion ::= type_mark ( expression ) type_declaration ::= full_type_declaration | incomplete_type_declaration type_definition ::= scalar_type_definition | composite_type_definition | access_type_definition | file_type_definition | protected_type_definition type_mark ::= type_name | subtype_name unconstrained_array_definition ::= array ( index_subtype_definition { , index_subtype_definition } ) of element_subtype_indication use_clause ::= use selected_name { , selected_name } ; variable_assignment_statement ::= [ label : ] target := expression ; variable_declaration ::= [ shared ] variable identifier_list : subtype_indication [ := expression ] ; wait_statement ::= [ label : ] wait [ sensitivity_clause ] [ condition_clause ] [ timeout_clause ] ; waveform ::= waveform_element { , waveform_element } | unaffected waveform_element ::= value_expression [ after time_expression ] | null [ after time_expression ] [ 8.1] [ 7.3.5] [ 4.1] [ 4.1] [ 4.2] [ 3.2.1] [ 10.4] [ 8.5] [ 4.3.1.3] [ 8.1] [ 8.4] [ 8.4.1] 236 Copyright 2000, IEEE. All rights reserved. This is an unapproved IEEE Standards Draft, subject to change. Annex A ...
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This note was uploaded on 09/09/2009 for the course EECS 318 taught by Professor Saab during the Fall '01 term at Case Western.

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