faq1 - comp.lang.vhdl Frequently Asked Questions And...

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comp.lang.vhdl Frequently Asked Questions And Answers (Part 1): General Preliminary Remarks This is a monthly posting to comp.lang.vhdl containing general information. Please send additional information directly to the editor: edwin@ds.e-technik.uni-dortmund.de (Edwin Naroska) Corrections and suggestions are appreciated. Thanks for all corrections. There are three other regular postings: part 2 lists books on VHDL, part 3 lists products and services (PD+commercial), part 4 contains descriptions for a number of terms and phrases used to define VHDL.
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Table of Contents . . . . . . . . . . . . 1 0. General Information/Introduction . . . . . . . . . . . . 1 0.1 The Group - Why and What . . . . . . . . . . . . . . . 1 0.2 What Is VHDL . . . . . . . . . . . . . . . 1 0.3 Before Posting . . . . . . . . . . . . 2 0.4 Major Contributors to this FAQ . . . . . . . . . . . . . . . . 2 0.5 Disclaimer . . . . . . . . . . . . . . . . 3 1. Abbreviations . . . . . . . . . . . . . . . 4 2. Contacts and Archives . . . . . . . . . . . . . . . 4 2.1 Official Contacts . . . . . . . . . . . . . . . . . 4 Accellera . . . . . . . . . . . . . . 4 VHDL International . . . . . . . . . . . 4 VHDL-AMS, 1076.1 Working Group . . . . . . . . . . . . . . . 5 WAVES/TISSS . . . . . . . . . . . . . . 5 2.2 VHDL User Groups . . . . . . . . . . . 5 VHDL International Users Forum . . . . . . . . . . . . . . . . . 6 2.3 Archives . . . . . . . . . . . . . . . 7 3. VHDL on the Web . . . . . . . . . . . . . . . . . 7 3.1 Tutorials . . . . . . . . . . . . . . . 7 3.2 VHDL Models . . . . . . . . . . . . . . . . 9 3.3 Magazines . . . . . . . . . . . . . . . . 9 3.4 VHDL Sites . . . . . . . . . . . . . 10 4. Frequently Asked Questions . . . . . . . . . . 10 4.1 About Changes to the VHDL Standard . . . . . . . . . . . . 10 4.2 Language Related Questions . . . . . . . . . . . . 10 4.2.1 USE of Library Elements? . . . . . 10 4.2.2 Component Instantiation and Default Component Binding . . . . . . . . . 15 4.2.3 GENERATE Usage and Configuration . . . . . . . 16 4.2.4 Aggregates/Arrays Containing a Single Element . . . . . . . . . . 17 4.2.5 Operations With Array Aggregates . . . . . . . . 19 4.2.6 How to Attach Attributes Inside of Generate . . . . . . . . . . . . 19 4.2.7 Notes on Range Directions . . . . . . . . . . . . 20 4.2.8 Integer - Time Conversion . . . . . . . . . . . . 20 4.2.9 "Don’t Cares" in VHDL . . . . . . . . . . . 21 4.2.10 How to Open and Close Files . . . . . . . . . . 23 4.2.11 How to Read/Write Binary Files . . . . . . 23 4.2.12 How to Use Package Textio for Accessing Text Files . . . . . . . . . . . . . . 27 4.2.13 Signal Drivers . . . . . . . . . . . . 30 4.2.14 Procedures and Drivers . . . . . . . . . . . . . . 31 4.2.15 Case Statement . . . . . . . . . . . . 32 4.2.16 How to Monitor Signals - i - Table of Contents FAQ comp.lang.vhdl (part 1) : General
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. . . . . . 34 4.2.17 Resolving Ambiguous Procedure/Function/Operator Calls . . . . . . . 35 4.2.18 How to Resolve Type Ambiguities in Expressions
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This note was uploaded on 09/09/2009 for the course EECS 318 taught by Professor Saab during the Fall '01 term at Case Western.

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faq1 - comp.lang.vhdl Frequently Asked Questions And...

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