eecs_318_sim_2

eecs_318_sim_2 - EECS 318 CAD EECS 318 CAD Computer Aided...

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Unformatted text preview: EECS 318 CAD EECS 318 CAD Computer Aided Design Computer Aided Design LECTURE Simulator 2: LECTURE Simulator 2: Textio, Wait, Clocks, and Textio, Wait, Clocks, and Test Benches Test Benches Instructor: Francis G. Wolff wolff@eecs.cwru.edu Case Western Reserve University CWRU EECS 318 This presentation uses powerpoint animation: please viewshow adder_full_tb_io.vhd: full adder test bench use STD.TextIO.ALL; use STD.TextIO.ALL; LIBRARY IEEE; LIBRARY IEEE; use IEEE.std_logic.all; use IEEE.std_logic.all; use IEEE.std_logic_textio.all; use IEEE.std_logic_textio.all; Note: in order to use Note: in order to use i/o, additional i/o, additional libraries must be libraries must be included included ENTITY adder_full_tb_io IS ENTITY adder_full_tb_io IS END; END; This test bench This test bench contains no outputs contains no outputs CWRU EECS 318 adder_full_tb_io.vhd: architecture begin ARCHITECTURE adder_full_tb_io_arch ARCHITECTURE adder_full_tb_io_arch OF adder_full_tb_io IS OF adder_full_tb_io IS COMPONENT adder_full COMPONENT adder_full PORT (x,y,Cin: IN std_logic; Sum,Cout: OUT std_logic); PORT (x,y,Cin: IN std_logic; Sum,Cout: OUT std_logic); END COMPONENT; END COMPONENT; SIGNAL x, y, Cin, Sum, Cout: std_logic; SIGNAL x, y, Cin, Sum, Cout: std_logic; BEGIN BEGIN UUT_ADDER: adder_full PORT MAP(x, y, Cin, Sum, Cout); UUT_ADDER: adder_full PORT MAP(x, y, Cin, Sum, Cout); CWRU EECS 318 adder_full_tb_io.vhd: test case #1 PROCESS PROCESS VARIABLE S: LINE; --used for write line buffer VARIABLE S: LINE; --used for write line buffer BEGIN BEGIN -- Test Case #1 -- Test Case #1 x<= '0'; y<= '1'; Cin<= '0'; x<= '0'; y<= '1'; Cin<= '0'; WAIT FOR 5 ns; WAIT FOR 5 ns; WRITE(S,STRING'(" X=")); WRITE(S, x); WRITE(S,STRING'(" X=")); WRITE(S, x); WRITE(S,STRING'(" Y=")); WRITE(S, y); WRITE(S,STRING'(" Y=")); WRITE(S, y); WRITE(S,STRING'(" Cin=")); WRITE(S, Cin); WRITE(S,STRING'(" Cin=")); WRITE(S, Cin); WRITE(S,STRING'(" Sum=")); WRITE(S, Sum); WRITE(S,STRING'(" Sum=")); WRITE(S, Sum); WRITE(S,STRING'(" Cout=")); WRITE(S, Cout); WRITE(S,STRING'(" Cout=")); WRITE(S, Cout); WRITELINE(OUTPUT, S); WRITELINE(OUTPUT, S); CWRU EECS 318 adder_full_tb_io.vhd: test case #2 -- Test Case #2 -- Test Case #2 x<= '1'; y<= '1'; Cin<= '0'; x<= '1'; y<= '1'; Cin<= '0'; WAIT FOR 5 ns; WAIT FOR 5 ns; WRITE(S,STRING'(" X=")); WRITE(S,STRING'(" X=")); WRITE(S,STRING'(" Y=")); WRITE(S,STRING'(" Y=")); WRITE(S,STRING'(" Cin=")); WRITE(S,STRING'(" Cin=")); WRITE(S,STRING'(" Sum=")); WRITE(S,STRING'(" Sum=")); WRITE(S,STRING'(" Cout=")); WRITE(S,STRING'(" Cout=")); WRITELINE(OUTPUT, S); WRITELINE(OUTPUT, S); WRITE(S, x); WRITE(S, x); WRITE(S, y); WRITE(S, y); WRITE(S, Cin); WRITE(S, Cin); WRITE(S, Sum); WRITE(S, Sum); WRITE(S, Cout); WRITE(S, Cout); CWRU EECS 318 adder_full_tb_io.vhd: configuration ASSERT FALSE ASSERT FALSE REPORT "Simulation Done" REPORT "Simulation Done" SEVERITY ERROR; SEVERITY ERROR; END PROCESS; END PROCESS; END ARCHITECTURE; END ARCHITECTURE; CONFIGURATION adder_full_tb_io_cfg OF CONFIGURATION adder_full_tb_io_cfg OF adder_full_tb_io IS adder_full_tb_io IS FOR adder_full_tb_io_arch FOR adder_full_tb_io_arch END FOR; END FOR; END CONFIGURATION; END CONFIGURATION; CWRU EECS 318 VHDL Simulator: running the test bench Unix> vhdlan -NOEVENT adder_full.vhd Unix> vhdlan -NOEVENT adder_full_tb_io.vhd Unix> vhdlsim WORK.adder_full_tb_io_cfg # ls ADDER_FULL_TB_IO STANDARD STD_LOGIC_1164 _KERNEL ATTRIBUTES # run X=0 Y=1 Cin=0 Sum=1 Cout=0 X=1 Y=1 Cin=0 Sum=0 Cout=1 10 NS Assertion ERROR at 10 NS in design unit ADDER_FULL_TB_IO(ADDER_FULL_TB_IO_ARCH) from process /ADDER_FULL_TB_IO/_P0: "Simulation Done" # quit CWRU EECS 318 VHDL clock behavioral component ENTITY clock_driver IS ENTITY clock_driver IS GENERIC (Speed: TIME := 5 ns); GENERIC (Speed: TIME := 5 ns); PORT (Clk: OUT std_logic); PORT (Clk: OUT std_logic); END; END; ARCHITECTURE clock_driver_arch OF clock_driver IS ARCHITECTURE clock_driver_arch OF clock_driver IS SIGNAL Clock: std_logic := `0'; SIGNAL Clock: std_logic := `0'; BEGIN BEGIN Clk <= Clk XOR `1' after Speed; Clk <= Clk XOR `1' after Speed; Clock <= Clk; Clock <= Clk; END ARCHITECTURE; END ARCHITECTURE; CONFIGURATION clock_driver_cfg OF clock_driver IS CONFIGURATION clock_driver_cfg OF clock_driver IS FOR clock_driver_arch END FOR; FOR clock_driver_arch END FOR; END CONFIGURATION; END CONFIGURATION; CWRU EECS 318 Team Assignment #5 Test benches (1/2) Display all input and output bits Three tests with correct results for each test bench Cut and Paste the output to a file and print it System Level: Team member #1 is responsible for T101_ALU_BIT_TB.vhd and T101_ALU_TB.vhd Processor: Team member #2 is responsible for T101_FSM_TB.vhd: test bench for add instruction Memory: Team member #3 is responsible for T101_RAM_TB.vhd write and read some words T101_ROM_TB.vhd with machine instructions CWRU EECS 318 Team Assignment #5 Test Bench (2/2) The report should contain the following Cover sheet Each entity section should have the vhdl, and simulation The VHDL test benches for the complete design Everything is due Thursday October 26! CWRU EECS 318 Team Assignment #6 System Test Bench The report should contain the following Cover sheet Each entity section should have the vhdl, simulation, and synthesis The vhdl T101_PU_TB.vhd test benches Simulate the 32 bit add program: output = input + 1 Read first byte value from the input port and zero upper 24 bits via lbi's Load the second value from immediate loads Store the results in the output port Display the output port in the test bench Combined report of Assignments #3, #4, #5 Everything is due Thursday October 26! CWRU EECS 318 ...
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This note was uploaded on 09/09/2009 for the course EECS 318 taught by Professor Saab during the Fall '01 term at Case Western.

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