eecs_318_sim_1

eecs_318_sim_1 - EECS 318 CAD EECS 318 CAD Computer Aided...

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CWRU EECS 318 EECS 318 CAD Computer Aided Design EECS 318 CAD Computer Aided Design LECTURE Simulator 1: Synopsys Simulator LECTURE Simulator 1: Synopsys Simulator Instructor: Francis G. Wolff [email protected] Case Western Reserve University This presentation uses powerpoint animation: please viewshow
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CWRU EECS 318 The adder file test bench hierarchy adder_full.vhd adder_full_tb.vhd
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CWRU EECS 318 adder_full.vhd: full 1-bit adder ARCHITECTURE adder_full_arch OF adder_full IS BEGIN Sum <= ( x XOR y ) XOR Cin ; Cout <= ( x AND y ) OR ( Cin AND ( x OR y )); END; CONFIGURATION adder_full_cfg OF adder_full IS FOR adder_full_arch END FOR; END CONFIGURATION; LIBRARY IEEE; use IEEE.std_logic_1164.all; ENTITY adder_full IS PORT ( x , y , Cin : IN std_logic; Sum , Cout : OUT std_logic ); END;
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CWRU EECS 318 VHDL analyzer: vhdlan For example: > vhdlan -NOEVENT adder_full.vhd Synopsys 1076 VHDL Analyzer Version 2000.06--May 24, 2000 Copyright (c) 1990-2000 by Synopsys, Inc. ALL RIGHTS RESERVED This program is proprietary and confidential information of Synopsys, Inc. and may be used and disclosed only as authorized in a license agreement controlling such use and disclosure. Unix command: vhdlan -NOEVENT <filename.vhd> Must be done to every vhdl file in the design
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CWRU EECS 318 VHDL Simulator: vhdlsim Unix command: vhdlsim <vhdl_configuration_name> Starts the text based vhdl simulator For example: > vhdlsim adder_full_cfg Synopsys 1076 VHDL Simulator Version 2000.06-- May 24, 2000 Copyright (c) 1990-2000 by Synopsys, Inc. ALL RIGHTS RESERVED This program is proprietary and confidential information of Synopsys, Inc. and may be used and disclosed only as authorized in a license agreement controlling such use and disclosure.
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This note was uploaded on 09/09/2009 for the course EECS 318 taught by Professor Saab during the Fall '01 term at Case Western.

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eecs_318_sim_1 - EECS 318 CAD EECS 318 CAD Computer Aided...

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