eecs_318_10 - EECS 318 CAD EECS 318 CAD Computer Aided...

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EECS 318 CAD Computer Aided Design EECS 318 CAD Computer Aided Design LECTURE 10: Improving Memory Access: Direct and Spatial caches LECTURE 10: Improving Memory Access: Direct and Spatial caches Instructor: Francis G. Wolff wolff@eecs.cwru.edu Case Western Reserve University This presentation uses powerpoint animation: please viewshow
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The Art of Memory System Design Processor $ MEM Memory reference stream <op,addr>, <op,addr>,<op,addr>,<op,addr>, . . . op: i-fetch, read, write Optimize the memory system organization to minimize the average memory access time for typical workloads Workload or Benchmark programs
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Pipelining and the cache (Designing…,M.J.Quinn, ‘87) Instruction Pipelining is the use of pipelining to allow more than one instruction to be in some stage of execution at the same time. Ferranti ATLAS (1963) : Pipelining reduced the average time per instruction by 375% Memory could not keep up with the CPU, needed a cache. Cache memory is a small, fast memory unit used as a buffer between a processor and primary memory
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Principle of Locality • Principle of Locality states that programs access a relatively small portion of their address space at any instance of time • Two types of locality • Temporal locality (locality in time) If an item is referenced, then the same item will tend to be referenced soon “the tendency to reuse recently accessed data items” • Spatial locality (locality in space) If an item is referenced, then nearby items will be referenced soon “the tendency to reference nearby data items”
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Memory Hierarchy Registers Pipelining Cache memory Primary real memory Virtual memory (Disk, swapping) Faster Cheaper Cost $$$ More Capacity CPU
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Memory Hierarchy of a Modern Computer System By taking advantage of the principle of locality: Present the user with as much memory as is available in the cheapest technology. Provide access at the speed offered by the fastest technology. Control Datapath Secondary Storage (Disk) Processor Registers Main Memory (DRAM) Second Level Cache (SRAM) On-Chip Cache 1s 10,000,000s (10s ms) Speed (ns): 10s 100s 100s Gs Size (bytes): Ks Ms Tertiary Storage (Disk) 10,000,000,000s (10s sec) Ts
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Cache Memory Technology: SRAM 1 bit cell layout
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Memories Technology and Principle of Locality • Faster Memories are more expensive per bit Memory Technology Typical access time $ per Mbyte in 1997 SRAM 5-25 ns $100-$250 DRAM 60-120 ns $5-$10 Magnetic Disk 10-20 million ns $0.10-$0.20 • Slower Memories are usually smaller in area size per bit
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Cache Memory Technology: SRAM • Why use SRAM (Static Random Access Memory)?
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eecs_318_10 - EECS 318 CAD EECS 318 CAD Computer Aided...

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