eecs_318_8 - EECS 318 CAD EECS 318 CAD Computer Aided...

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CWRU EECS 318 EECS 318 CAD Computer Aided Design EECS 318 CAD Computer Aided Design LECTURE 8: VHDL PROCESSES LECTURE 8: VHDL PROCESSES Instructor: Francis G. Wolff wolff@eecs.cwru.edu Case Western Reserve University This presentation uses powerpoint animation: please viewshow
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CWRU EECS 318 2-to-1 Multiplexor: and Datapath multiplexor 0 1 a b S Y WITH s SELECT Y <= a WHEN ‘0’, b WHEN OTHERS; behavioral WITH s SELECT Y <= a WHEN ‘0’, b WHEN OTHERS; Datapath is n bits wide Where is the difference? 0 1 a b S Y n n n
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CWRU EECS 318 Generic 2-to-1 Datapath Multiplexor Entity 0 1 a b S Y n n n LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.std_logic_arith.all; ENTITY Generic_Mux IS GENERIC ( n : INTEGER); PORT ( Y : OUT std_logic_vector( n -1 downto 0); a : IN std_logic_vector( n -1 downto 0); b : IN std_logic_vector( n -1 downto 0); S : IN std_logic_vector(0 downto 0) ); END ENTITY;
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CWRU EECS 318 Generic 2-to-1 Datapath Multiplexor Architecture ARCHITECTURE Generic_Mux_arch OF Generic_Mux IS BEGIN WITH S SELECT Y <= a WHEN "1", b WHEN OTHERS; END ARCHITECTURE; Configurations are require for simulation CONFIGURATION Generic_Mux_cfg OF Generic_Mux IS FOR Generic_Mux_arch END FOR; END CONFIGURATION;
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CWRU EECS 318 Structural SR Flip-Flop (Latch) NAND R S Q n+1 0 0 U 0 1 1 1 0 0 1 1 Q n R S Q Q ENTITY Latch IS PORT( R, S : IN std_logic; Q, NQ : OUT std_logic); END ENTITY; ARCHITECTURE latch_arch OF Latch IS BEGIN Q <= R NAND NQ ; NQ <= S NAND Q ; END ARCHITECTURE;
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CWRU EECS 318 Inferring Behavioral Latches: Asynchronous ARCHITECTURE Latch2_arch OF Latch IS BEGIN PROCESS ( R , S ) BEGIN IF R = ‘0’ THEN Q <= ‘1’; NQ <= ‘0’; ELSIF S = ‘0’ THEN Q <= ‘0’; NQ <= ‘1’; END IF; END PROCESS; END ARCHITECTURE; NAND R S Q n+1 0 0 U 0 1 1 1 0 0 1 1 Q n R S Q Q Sensitivity list of signals: Every time a change of state or event occurs on these signals this process will be called Sequential Statements
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CWRU EECS 318 Gated-Clock SR Flip-Flop (Latch Enable) S R Q Q LE ARCHITECTURE Latch_arch OF GC_Latch IS BEGIN PROCESS ( R , S, LE) BEGIN IF LE = ‘1’ THEN IF R = ‘0’ THEN Q <= ‘1’; NQ <= ‘0’; ELSIF S = ‘0’ THEN Q <= ‘0’; NQ <= ‘1’; END IF; END IF; END PROCESS; END ARCHITECTURE;
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CWRU EECS 318 Inferring D-Flip Flops: Synchronous ARCHITECTURE Dff_arch OF Dff IS BEGIN PROCESS ( Clock ) BEGIN IF Clock
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This note was uploaded on 09/09/2009 for the course EECS 318 taught by Professor Saab during the Fall '01 term at Case Western.

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eecs_318_8 - EECS 318 CAD EECS 318 CAD Computer Aided...

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