eecs_318_5 - EECS 318 CAD EECS 318 CAD Computer Aided...

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Unformatted text preview: EECS 318 CAD EECS 318 CAD Computer Aided Design Computer Aided Design LECTURE 5: LECTURE 5: AOIs, AOIs, WITH-SELECT-WHEN, WITH-SELECT-WHEN, WHEN-ELSE WHEN-ELSE Instructor: Francis G. Wolff wolff@eecs.cwru.edu Case Western Reserve University This presentation uses powerpoint animation: please viewshow CWRU EECS 318 DeMorgan's laws: review X Y=X+Y General Rule: 1. Exchange the AND with OR 2. Invert the NOTs X Y=X+Y X+Y=X Y X+Y=X Y CWRU EECS 318 CMOS logic gate: review 4 transistors 4 transistors 2 transistors CWRU EECS 318 CMOS logic gate: layout sizes (1X output drive) CWRU EECS 318 AOI: AND-OR-Invert gates Suppose you want to transform a circuit to all nands & nots 6 6 16 transistors 4 4 4 2 2 4 4 4 4 Final 14 Transistors Final 14 Transistors 2 CWRU EECS 318 AOI: AND-OR-Invert gates Although, there were no tricks to make AND gates better AOIs provide a way at the gate level to use less transistors than separate ANDs and a NORs ASIC design logic builds upon a standard logic cell library, therefore, do not optimize transistors only logic gates For example, 2-wide 2-input AOI will only use 8 transistors 4 4 4 2 Whereas 2 ANDs (12 transistors) and 1 NOR (4 transistors) will use a total of 16 transistors {14 by DeMorgans law} CWRU EECS 318 AOI: AND-OR-Invert cmos 2x2 example For example, 2-wide 2-input AOI (2x2 AOI) O <= NOT((D1 AND C1) NOR (B1 AND A1)); CWRU EECS 318 AOI: AND-OR-Invert cmos 2x2 example This means AOIs use less chip area, less power, and delay CWRU EECS 318 AOI: other Standard Cell examples AOI22 Cell: 2x2 AOI (8 transistors) Y <= (A AND B) NOR (C AND D); AOI23 Cell: 2x3 AOI (10 transistors) Y <= (A AND B) NOR (C AND D AND E); AOI21 Cell: 2x1 AOI (6 transistors) Y <= (A AND B) NOR C; Total transistors = 2 times # inputs CWRU EECS 318 AOI: XOR implementation 8 8 6 The XOR is not as easy as it appears Y <= (A AND NOT B) OR (NOT B AND A); This design uses 22 transistors Y <= NOT( A XNOR B); 6 8 4 Y <= NOT( (A AND B) OR (NOT B AND NOT A)); This newer design uses 18 transistors But wait, we can exploit the AOI22 structure now we have 4+4+2+2=12 transistors 4 4 2 Y <= NOT( (A AND B) OR (B NOR A) ); Finally, by applying DeMorgan's law The total of transistors is now 10 CWRU EECS 318 OAI: Or-And-Invert Or-And-Inverts are dual of the AOIs CWRU EECS 318 with-select-when: 2-to-1 Multiplexor a 6 2 structural 6 Y a 0 1 behavioral Y b b 6 S 20 Transistors S Only Only values values allowed allowed Y <= (a AND NOT s) Y <= (a AND NOT s) OR OR (b AND s); (b AND s); combinatorial logic WITH s SELECT WITH s SELECT Y <= a WHEN `0', Y <= a WHEN `0', b WHEN `1'; b WHEN `1'; or alternatively WITH s SELECT WITH s SELECT Y <= a WHEN `0', Y <= a WHEN `0', b WHEN OTHERS; b WHEN OTHERS; CWRU EECS 318 with-select-when: 2 to 4-line Decoder 6 8 8 10 S1 S0 Y3 Y2 Y1 Y0 S1 S0 Y3 Y2 Y1 Y0 SIGNAL S: std_logic_vector(1 downto 0); SIGNAL S: std_logic_vector(1 downto 0); SIGNAL Y: std_logic_vector(3 downto 0); SIGNAL Y: std_logic_vector(3 downto 0); 32 Transistors WITH S SELECT WITH S SELECT Replace this Replace this with a NOR, with a NOR, then 26 total then 26 total transistors transistors Y <= "1000" WHEN "11", Y <= "1000" WHEN "11", "0100" WHEN "10", "0100" WHEN "10", "0010" WHEN "01", "0010" WHEN "01", "0001" WHEN OTHERS; "0001" WHEN OTHERS; CWRU EECS 318 ROM: 4 byte Read Only Memory A1 A0 Y3 Y2 Y1 Y0 4 byte by 8 bit ROM ARRAY OE D7 D6 D5 D4 D3 D2 D1 D0 CWRU EECS 318 ROM: 4 byte Read Only Memory ENTITY rom_4x8 IS ENTITY rom_4x8 IS PORT(A: IN std_logic_vector(1 downto 0); PORT(A: IN std_logic_vector(1 downto 0); OE: IN std_logic; -- Tri-State Output OE: IN std_logic; -- Tri-State Output D: OUT std_logic_vector(7 downto 0) D: OUT std_logic_vector(7 downto 0) ); END; ); END; ARCHITECTURE rom_4x8_arch OF rom_4x8 IS ARCHITECTURE rom_4x8_arch OF rom_4x8 IS SIGNAL ROMout: std_logic_vector(7 downto 0); SIGNAL ROMout: std_logic_vector(7 downto 0); BEGIN BEGIN BufferOut: TriStateBuffer GENERIC MAP(8) BufferOut: TriStateBuffer GENERIC MAP(8) PORT MAP(D, ROMout, OE); PORT MAP(D, ROMout, OE); WITH A SELECT WITH A SELECT ROMout <= "01000001" WHEN "00", ROMout <= "01000001" WHEN "00", "11111011" WHEN "01", "11111011" WHEN "01", "00000110" WHEN "10", "00000110" WHEN "10", "00000000" WHEN "11"; "00000000" WHEN "11"; CWRU EECS 318 when-else: 2-to-1 Multiplexor WITH s SELECT WITH s SELECT Y <= a WHEN `0', Y <= a WHEN `0', b WHEN `1'; b WHEN `1'; WITH s SELECT WITH s SELECT Y <= a WHEN `0', Y <= a WHEN `0', b WHEN OTHERS; b WHEN OTHERS; a 0 Y b 1 Y <= a WHEN s = `0' ELSE Y <= a WHEN s = `0' ELSE b WHEN s = `1'; b WHEN s = `1'; or alternatively Y <= a WHEN s = `0' ELSE Y <= a WHEN s = `0' ELSE b; b; WHEN-ELSE condition WHEN-ELSE condition allows a condition as part allows a condition as part of the WHEN of the WHEN whereas the WITH-SELECT whereas the WITH-SELECT only allows only a value as only allows only a value as part of the WHEN. part of the WHEN. CWRU EECS 318 S with-select-when: 4-to-1 Multiplexor a b c d 00 01 10 11 Y WITH s SELECT WITH s SELECT Y <= a WHEN "00", Y <= a WHEN "00", b WHEN "01", b WHEN "01", c WHEN "10", c WHEN "10", d WHEN OTHERS; d WHEN OTHERS; Y <=a WHEN s = "00" ELSE Y <=a WHEN s = "00" ELSE b WHEN s = "01" ELSE b WHEN s = "01" ELSE c WHEN s = "10" ELSE c WHEN s = "10" ELSE d ;; d S As long as each WHENAs long as each WHENELSE condition is ELSE condition is mutually exclusive, mutually exclusive, then it is equivalent to then it is equivalent to the WITH-SELECT the WITH-SELECT statement. statement. CWRU EECS 318 when-else: 2-level priority selector a 6 6 Y b 10 22 Transistors S1 S0 Y <= a WHEN s(1) = `1' Y <= a WHEN s(1) = `1' ELSE ELSE b WHEN s(0) = `1' b WHEN s(0) = `1' ELSE ELSE `0'; `0'; WITH s SELECT WITH s SELECT Y <= a WHEN "11", Y <= a WHEN "11", a WHEN "10", a WHEN "10", b WHEN "01", b WHEN "01", `0' WHEN OTHERS; `0' WHEN OTHERS; WHEN-ELSE are useful for WHEN-ELSE are useful for sequential or priority sequential or priority encoders encoders WITH-SELECT-WHEN are WITH-SELECT-WHEN are useful for parallel or useful for parallel or multiplexors multiplexors CWRU EECS 318 when-else: 3-level priority selector a 6 8 10 b c 14 S2 S1 S0 22 Transistors WITH s SELECT WITH s SELECT Y <= a WHEN "111", Y <= a WHEN "111", a WHEN "110", Y a WHEN "110", a WHEN "101", a WHEN "101", a WHEN "100", a WHEN "100", b WHEN "011", b WHEN "011", b WHEN "010", b WHEN "010", c WHEN "001", c WHEN "001", `0' WHEN OTHERS; `0' WHEN OTHERS; Y <= a WHEN s(2) = `1' ELSE Y <= a WHEN s(2) = `1' ELSE b WHEN s(1) = `1' ELSE b WHEN s(1) = `1' ELSE c WHEN s(0) = `1' ELSE c WHEN s(0) = `1' ELSE `0'; `0'; CWRU EECS 318 when-else: 2-Bit Priority Encoder (~74LS148) Priority encoders are typically used as interrupt controllers The example below is based on the 74LS148 I3 I2 I1 I0 GS A1 A0 II3 3 0 0 1 1 1 1 1 1 1 1 II2 2 X X 0 0 1 1 1 1 1 1 II1 1 X X X X 0 0 1 1 1 1 II0 0 X X X X X X 0 0 1 1 GSS G 0 0 0 0 0 0 0 0 1 1 A11 A 0 0 0 0 1 1 1 1 1 1 A00 A 0 0 1 1 0 0 1 1 1 1 CWRU EECS 318 when-else: 2-Bit Priority Encoder (~74LS148) I3 I2 I1 I0 GS A1 A0 ENTITY PriEn2 IS PORT( ENTITY PriEn2 IS PORT( I: IN std_logic_vector(3 downto 0); I: IN std_logic_vector(3 downto 0); GS: OUT std_logic; GS: OUT std_logic; A: OUT std_logic_vector(1 downto 0); A: OUT std_logic_vector(1 downto 0); ); END; ); END; II3 II2 II1 II0 3 2 1 0 0 0 1 1 1 1 1 1 1 1 X X X X X X 0 X X 0 X X 1 0 X 1 0 X 1 1 0 1 1 0 1 1 1 1 1 1 GS A1 A0 GS A1 A0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 1 1 A <= "00" WHEN II3= 0 ELSE A <= "00" WHEN 3 = 0 ELSE "01" WHEN II2= 0 ELSE "01" WHEN 2 = 0 ELSE "10" WHEN II1= 0 ELSE "10" WHEN 1 = 0 ELSE "11" WHEN II0= 0 ELSE "11" WHEN 0 = 0 ELSE "11" WHEN OTHERS; "11" WHEN OTHERS; CWRU EECS 318 when-else: 2-Bit Priority Encoder (~74LS148) I3 I2 I1 I0 GS A1 A0 Structural model GS <= NOT( NOT(I33)OR NOT(I22) GS <= NOT( NOT(I ) OR NOT(I ) OR NOT(I11)OR NOT(I00))) OR NOT(I ) OR NOT(I ) Structural model GS <= II3 AND II2AND II1AND II0 GS <= 3 AND 2 AND 1 AND 0 Behavioral model GS <= WITH IISELECT GS <= WITH SELECT `1' WHEN "1111", `1' WHEN "1111", `0' WHEN OTHERS; `0' WHEN OTHERS; CWRU EECS 318 II3 II2 II1 II0 3 2 1 0 0 0 1 1 1 1 1 1 1 1 X X X X X X 0 X X 0 X X 1 0 X 1 0 X 1 1 0 1 1 0 1 1 1 1 1 1 GS A1 A0 GS A1 A0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 1 1 ...
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