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eecs_318_4

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CWRU EECS 318 EECS 318 CAD Computer Aided Design EECS 318 CAD Computer Aided Design LECTURE 4: Delay models & std_ulogic LECTURE 4: Delay models & std_ulogic Instructor: Francis G. Wolff [email protected] Case Western Reserve University This presentation uses powerpoint animation: please viewshow

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CWRU EECS 318 Delta Delay
CWRU EECS 318 Delta Delay: Example using scheduling

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CWRU EECS 318 Inertial Delay
CWRU EECS 318 Transport Delay

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CWRU EECS 318 Inertial and Transport Delay Sig a b Inertial Delay is useful for modeling logic gates Transport Delay is useful for modeling data buses, networks
CWRU EECS 318 Combinatorial Logic Operators AND z <= x AND y; NAND z <= NOT (x AND y); NOR z <= NOT (x OR Y); OR z <= x OR y; NOT z <= NOT (x); z<= NOT x; XOR z <= (x and NOT y) OR (NOT x AND y); z <= (x AND y) NOR (x NOR y); --AOI XNOR z <= (x and y) OR (NOT x AND NOT y); z <= (x NAND y) NAND (x OR y); --OAI 2 2+2 i 2 i 2+2 i 2 i 10 10 #Transistors Footnote: (i=#inputs) We are only referring to CMOS static transistor ASIC gate designs Exotic XOR designs can be done in 6 (J. W. Wang, IEEE J. Solid State Circuits, 29, July 1994)

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CWRU EECS 318 Std_logic AND: Un-initialized value AND 01U 0000 101U U0 UU OR 001U 1111 UU1 U 0 AND <anything> is 0 0 NAND <anything> is 1 1 OR <anything> is 1 1 NOR <anything> is 0 NOT 10U
CWRU EECS 318 Std_logic AND: X Forcing Unknown Value AND 0X 1U 00000 X0 XXU 10X U0 UUU 0 AND <anything> is 0 0 NAND <anything> is 1 OR 00X XXX1 U 11111 UUU1 U 1 OR <anything> is 0 0 NOR <anything> is 1 NOT 1X 0U

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