dft_vhdl_guidelines_infineon

dft_vhdl_guidelines_infineon - t e c h n o l o g i e s...

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Unformatted text preview: t e c h n o l o g i e s Infineon Chapter SC Highway Release 2.1, June 26, 2000 Application Notes 1 1 Application Notes 1 VHDL Coding Guidelines SC Highway Release 2.1, June 26, 2000 VHDL Coding Guidelines Application Notes 2 t e c h n o l o g i e s Infineon 1.1 Introduction Coding of design behaviour and architecture is one of the most important steps in the whole chip design project. It has major impact on logic synthesis and routing results, timing robustness, ver- ifiability, testability and even product support. The VHDL Coding Guidelines help chip and macro development teams to rapidly understand each other's code. Macro based designs integrate easier, if these common coding styles are followed. This also applies to externally developed softcores. Codes will not need modification if simulator, synthesis tool or technology is exchanged. Code invariance wrt. Synthesis tool is given in case of a similar VHDL synthesis subset. Code invariance wrt. technology is given in case of similar per- formance and cell set. In addition the given guidelines enable high synthesis quality and simula- tion performance. The VHDL Coding Guidelines need continuous adaptation according to new tool properties and new upcoming methodologies. Please participate in this process with your design know-how. Direct your contributions and related questions to the SC Highway Frontend Hotline ( hwf e@hl.sie- mens .de , tel.: 24666). Contribute rules for VHDL coding, that turned out to prevent errors in the downstream flow, or recommendations, that alleviate further design, re-use or maintenance. The VHDL Coding Guidelines may be passed to sub-contractors or cooperation partners. Ideally their coding works should comply to these guidelines, enabling rapid and safe integration with internally developed modules. Reading of the VHDL Coding Guidelines is most efficient at the beginning of a chip-design-project. Furthermore " Ear ly Code Re vie w " should be considered in a very early phase of VHDL coding as a training measure. Up to now every designer is responsible to follow relevant rules. Automated checks are not yet available. However, it is planned, to integrate such a tool into SC Highway, which will then use the rules that are given here. t e c h n o l o g i e s Infineon Application Notes SC Highway Release 2.1, June 26, 2000 1.2 Rules by Topics 1 3 Application Notes 1.2 Rules by Topics Each item is marked according to the categories ❏ mandatory (m) ❏ strongly recommended (r) ❏ advisable (a) ❏ explanatory (e) 1.2.1 Compilation 1. Configuration must be in a separated file (m) 2. A configuration declaration is needed for each architecture (m). 3. Testbench and DUT should be compiled into the same library (a)....
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This note was uploaded on 09/09/2009 for the course EECS 318 taught by Professor Saab during the Fall '01 term at Case Western.

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dft_vhdl_guidelines_infineon - t e c h n o l o g i e s...

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