dft_gated_clock_design - EXPERT COLUMN EDA KISS those...

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November 1997 PERSONAL ENGINEERING 53 KISS those asynchronous-logic problems good-bye Steven K Knapp is the founder and president of OptiMagic Inc (Aptos, CA, www.optimagic.com), a firm that devel- ops intellectual property and design soft- ware for programmable logic. Prior to founding this firm he held various applica- tions, engineering and management posi- tions at Xilinx and Intel’s former program- mable-logic division. EXPERT COLUMN EDA (a) (b) Fig 1—Gated clocks often have glitches due to differences in signal arrival times (a). Changing to a synchronous solution guarantees success(b). Steve Knapp Many organizations promote an ef- fective philosophy dubbed KISS (for Keep It Simple, Stupid) to improve the success rate of complex opera- tions. A variation of this theme pro- motes success in digital design: Keep It Strictly Synchronous. The popularity and flexibility of array-based logic—whether a field- programmable gate array (FPGA), a complex programmable-logic device (CPLD) or a gate array—might tempt unwary designers into developing bad asynchronous habits. Because these devices all use programmable interconnect, different signal arrival times coupled with asynchronous logic invite a digital disaster. Synchronous designs are inher- ently safer and easier to debug than asynchronous designs. Engineers can simply predict the behavior of syn- chronous systems and model them in simulation. The analysis comes down to the worst-case path between clock edges—a simple process, especially using a static timing analyzer. Asyn- chronous design involves analyzing all combinations of best- and worst- case signal paths over temperature, voltage and process—a far more oner- ous chore. Consequently, synchronous de- signs work with a much wider varia- tion in device timing parameters and over a broader temperature range than do most asynchronous designs. As process technology improves, cir- cuit delays decrease. A vendor might ship faster devices that meet all datasheet specifications but behave differently than the old part. Prob- lems with asynchronous logic usu- ally don’t appear until you’ve built a board. One batch of parts works fine, another batch fails the system test,
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This note was uploaded on 09/09/2009 for the course EECS 318 taught by Professor Saab during the Fall '01 term at Case Western.

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dft_gated_clock_design - EXPERT COLUMN EDA KISS those...

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