dft_asic_guidelines_atmel - ASIC Design Guidelines...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
ASIC Design Guidelines Introduction The Atmel ASIC Design Guidelines constitute a general set of recommendations intended for use by designers when preparing circuits for fabrication by Atmel. The guidelines are independent of any particular CAD tool or silicon process. They are applicable to Gate Arrays, Cell-Based ASICs (CBICs) and full-custom designs. Although they do not give specific coding recommendations, they apply equally to designs captured in Verilog or VHDL as to designs captured as schematics. These guidelines do not cover general principles of ASIC design; rather they highlight specific design practices which are regarded as unsafe, and which can lead to devices which are difficult to test, and whose correct operation cannot be guaranteed under all circumstances. For each unsafe, and therefore non-recommended design practice, an alternative safe, and therefore recommended practice is proposed. The current paradigm shift towards system level integration (SLI), incorporating multi- ple complex functional blocks and a variety of memories on a single circuit, gives rise to a new set of design requirements at integration level. These design guidelines do not fully address these issues yet. The recommendations are principally aimed at the design of the blocks and memory interfaces which are to be integrated into the sys- tem-on-chip. However, the guidelines given here are fully consistent with the require- ments of system level integration. Respect for these guidelines will significantly ease the integration effort, and ensure that the individual blocks are easily reusable in other systems. These design guidelines have been drawn up in the light of experience with large numbers of ASIC designs over more than a decade. The Atmel ASIC Design Guidelines have a particular significance during the signoff of each design prior to submission for fabrication: Atmel customers must sign off a design to confirm that it complies with all the recom- mendations in the Atmel ASIC Design Guidelines. For each case of non-compliance, the case must be discussed with the ASIC Support Center, and if necessary a formal Authorization must be obtained. Application Specific IC (ASIC) Application Note Rev. 1205A–12/99 Design Guidelines
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
ASIC 2 Synchronous Circuits Experience has shown that the safest methodology for time-domain control of an ASIC is synchronous design . A synchronous circuit is one in which: all data storage elements are clocked, and in normal operation change state only in response to the clock signal the same active edge of a single clock signal is applied at precisely the same point in time at every clocked cell in the device. Examples of circuit elements which contradict these princi- ples are given below, and methods of achieving synchro- nous design are given in the four sections which follow.
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 09/09/2009 for the course EECS 318 taught by Professor Saab during the Fall '01 term at Case Western.

Page1 / 45

dft_asic_guidelines_atmel - ASIC Design Guidelines...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online