ee201l_debugging - EE201L - Introduction to Digital...

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EE201L - Introduction to Digital Circuits Experiment # 5 [Revised: 2/13/08] 1/8 Experiment # 5 Debugging via Simulation using Modelsim & Hardware Debugging using Chipscope 1. Synopsis: In this lab you will be debugging the number lock design. We have introduced different kinds of errors in the design purposefully to demonstrate various common errors made during schematic entry. You will find these errors by incrementally simulating the design and fixing the errors as they are revealed. You will also use Chipscope to probe the circuit to find some other errors and analyse the design. The key idea in this challenging lab is to learn how logic simulation tools and debugging tools can be used to debug complex digital circuits. 2. Lecture / Demo Video: Before coming for the lab session, you are required to watch the “Introduction to Chipscope” webcast (posted to the class website). It is a screen capture of an entire session of Xilinx Chip- scope - Core Generator / Analyzer starting from invoking the tool to trigger mechanism and view- ing the captured signals. 3. Introduction In this lab, you have been provided with a complete but erroneous design. The circuit has been designed in Xilinx Schematic Editor and we have provided a Verilog Test Fixture for the core design. Part 1: In Part 1 you have to incrementally simulate the core design using Modelsim. You have been provided with a test fixture for the core design. By looking at the waveform, you should be able to detect the sources of errors. Next, you will make necessary modifications to the design and simulate again till you are satisfied that the core design works for all the three test cases. Part 2: The top design is to be debugged by downloading the design on the board / viewing the signal values on Chipscope. As in debugging using simulation you need to identify the bug and make necessary modifications to the design and re-implement it. For the part 2 you will NOT be simulating the design (in Modelsim) at any time. Assume that the Modelsim tool is not working and that you need to debug the design in hardware!
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EE201L - Introduction to Digital Circuits Experiment # 5 [Revised: 2/13/08] 2/8 4. Common Errors: There are several errors in the design. This section should help you in understanding what sort of errors to look for in the design given to you. Each one of these errors falls into one of the following broad categories: 4.1 Wiring/drawing/labeling errors : These are errors made during the drawing of the circuit. Examples are unconnected pins, dangling wires (wires are also called ‘nets’) and misconnected wires (e.g., a wire that should be connected to VDD might be connected to GND). 4.2 Logical errors : The logic implemented to achieve a certain operation could be improper. Especially, watch out for such errors in simple basic building blocks . The building blocks (components) themselves may be erroneous! Note that you have to exhaustively test a circuit to locate such errors as it is possible that an erroneous circuit would work ‘ok’ for a certain input pattern but not for another.
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This note was uploaded on 09/12/2009 for the course EE 201L taught by Professor Puvvada during the Spring '08 term at USC.

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ee201l_debugging - EE201L - Introduction to Digital...

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