ee201l_numlock

ee201l_numlock - EE201L Introduction to Digital Circuits...

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Unformatted text preview: EE201L - Introduction to Digital Circuits Experiment # 6 ee201l_numlock.fm [Revised: 2/21/08] 1/16 Experiment # 6 Introduction to Verilog - Number Lock (Part II) 1. Synopsis: This lab introduces you to Verilog coding. You can consider this an “alternative” to designing schematics for now. Your efforts will focus around the number-lock design you saw in a previous lab. You will have the chance to see a complete solution for the Detour lab written entirely in Ver- ilog. Designing circuits in Verilog allows you to express your implementation at a much higher level. After completing this lab you should have a working knowledge of the syntax, you should possess the ability to debug Verilog code, and know the procedure to realize your Verilog code on an FPGA. The content from sections 2 & 3 excerpt from your earlier lab. You can refer to it later as neces- sary but pay special attention to the state machine diagram in section 3. 2. Description of the Circuit: In this lab our goal is to design a state machine to work as a Number Lock. Assume that on the Number Lock you have two push buttons, called UNO and ZERO. UNO in Spanish means ONE. Also, assume that two signals come out of the push button unit as input to the state machine and these are called U and Z. The U signal goes high when UNO is pressed and the Z signal goes high when the ZERO is pressed. If neither is pressed, both signals remain low. Assume that your state machine is clocked by approximately 10Hz clock (0.1 second per clock cycle). The actual clock used in your design is even slower. Humans tend to press a push button usually anywhere between a quarter second to half a second. So once your state machine detects that a push button is pressed it should wait until the button is released. It should not interpret a long push as multiple pushes. The binary Number Lock secret code is 1 0 1 1. If the sequence is wrong, the state machine should go back to the INITIAL state and start looking for the code afresh. That is to say, that if 101011 is pressed, the number lock will not open though the last four bits match with the code. This is because, after 1010 the machine goes back to the very beginning. Assume that the user does not normally press both the buttons together. This assumption simplifies the design a little bit. However, one should not succeed in opening the lock by pressing both the buttons together every time. 3. The State Diagram Here, you are provided with a complete state diagram. The state machine starts in the INITIAL state and as the user enters the Number Lock Code, by pressing UNO and ZERO buttons, the state machine goes through various states, each representing the sequence received so far. Note the naming convention followed in the state machine: state G1 means got a 1 . Preceding this state, we have G1GET which means that we are in the process of getting a 1 , meaning that the UNO button was pressed but has not been released yet. EE201L - Introduction to Digital Circuits...
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ee201l_numlock - EE201L Introduction to Digital Circuits...

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