ee102_midterm1_Sp2005

ee102_midterm1_Sp2005 - ee102_midterm1_Sp2005.fm Spring...

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ee102_midterm1_Sp2005.fm 4/1/05 EE102L Midterm #1 - Spring 2005 1 / 8 C Copyright 2005 Gandhi Puvvada Spring 2005 EE102L Instructor: Gandhi Puvvada Midterm Exam (15%) Date: April 1, 2004, Friday Open-Book Open-Notes Exam Time: 4:05 - 6:00PM in SGM124 Name: Total points: 155 Perfect score: 145 1 ( 4+6+10+5+6+4+6=41 points) 35 min. Combinational logic, etc.: 1.1 A _________________ (10 Kohm / 330 ohm) resistor is usually employed as current-limiting resistor in series with an LED. The sinking capability at the ___________ (output/input) of a __________________________________________ (totem-pole out put / open-collector output) gate is a better choice compared to the sourcing capability to drive an LED. In such cases, you produce a ____________ (0 / 1) to light up the LED. 1.2 It is NOT desirable that __________ ( VIH/VOH) is close to 5V . Similarly it is NOT desirable that ____________ ( VIL/VOL ) is close to 0V . We want _________ ( VIH/VIL ) to be higher than _________ ( VOH/VOL ) because _____________________________________________ ____________________________________________________________________________ ____________________________________________________________________________ 1.3 Given below are Shannon’s Expansion Theorems (covered in EE101 ?). F(X 1 , X 2 , . ...,X n ) = X1. F(1, X 2 , . ...,X n ) + X1’. F(0, X 2 , . ...,X n ) F(X 1 , X 2 , . ...,X n ) = [X1+ F(0, X 2 , . ...,X n ) ] . [X1’+ F(1, X 2 , . ...,X n )] Now consider the Carry-Out from a full-adder. Cout is a function of (X, Y, Cin) Cout = F(Cin, X, Y) = X . Cin + Y . Cin + X . Y = Cin . (X + Y) + X . Y If Cin = 0, then Cout = X . Y and if Cin = 1, then Cout = X + Y Based on the above, produce Cout by completing as many of the four logics as possible. 4 pts 6 pts FA X Y Cin Cout S 10 pts Cout Cin Cout Cin Cout Cin Cout Cin
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ee102_midterm1_Sp2005.fm 4/1/05 EE102L Midterm #1 - Spring 2005 2 / 8 C Copyright 2005 Gandhi Puvvada 1.4 A student tried to build two demuxes. He is not sure if any of them are right and if so whether they mach with any/multiple of the symbols on the right. State if there is match and label the inputs and outputs of the circuit(s) which matched. 1.5 Open-collector wire-ANDing to eliminate logic on the mother board: Mr. Bruin had the following logic on his mother board. He brought A, B, C, and D from 4 add-on cards, produced the result R and returned to each of the four cards. So, Mr. Trojan/Miss Trojan, how do you propose to improve the design to combine the 5 traces into one trace on the motherboard and also reduce two edge connection pins into one pin on each add-on card? Note: Like in your homework #3 solution (page 5/12), you are allowed to use inverters to suit. You would use Open-Collector gates (select one or more) (a) on the add-on cards to send signal to the mother board (b) on mother board to process the incoming signals and produce result (c) on add-on cards to receive the result from the mother board and further process it. 5 pts D0 S D D1 /D0 S D /D1 /D0 S /D /D1 D0 S /D D1 A B D C Matches with symbol ______ ( A / B / C / D / none) Matches with symbol ______ ( A / B / C / D / none) 6 pts A _ c a r d B C D R e s u lt M ot he r B o rd A D C B R Bruin’s logic on motherboard
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ee102_midterm1_Sp2005.fm 4/1/05 EE102L Midterm #1 - Spring 2005 3 / 8 C Copyright 2005 Gandhi Puvvada 1.6 Mr. Bruin wanted a decoder with active-high outputs but he
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This note was uploaded on 09/12/2009 for the course EE 201L taught by Professor Puvvada during the Spring '08 term at USC.

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ee102_midterm1_Sp2005 - ee102_midterm1_Sp2005.fm Spring...

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