ee102_midterm1_Sp2005_sol

ee102_midterm1_Sp2005_sol - ee102_midtennlMSp2005.fm Spring...

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Unformatted text preview: ee102_midtennlMSp2005.fm Spring 2005 EE102L Instructor: Gandhi Puvvada Midterm Exam (15%) Date: April 1, 2004, Friday Open-Book Open-Notes Exam Time: 4:05 - 6:00PM in SGM124 Name: O N Total points: i 55 5 Perfect score: fig *5 +213 3 is? , 1 ( geaafa +$eré3e is.” points)3§ min. Combinational logic, etc.: A 330 ohm (10 Kohm / 330 ohm) resistor is usually employed as current-limiting resistor in series with an LED. The sinking capability at the Q3 (output/input) of a tct%— pa in (3.4335: (totem—pole out put / open-collector output) gate is‘better choice compared to the sourcing capability to drive an LED. In such cases, you produce a g (0/ 1) to light up the LED. It is NOT desirable that V 1 H (VIH/VOH) is close to 5V. Similarly it is NOT desirable that V: L. (VIL/VOL) is close to 0V. We want V: L. (VIH/VIL) to be higher than VOL. (VdH/VGL) because V1; balm high“ W a; €01; a); flau- Vulgaqapg— Given below are Shannon’s Expansion Theorems (covered in EElOl ?). F(X1, X2, F(X1, X2, .,Xn) = X1. F(1, X2, .,Xn) = [X1+ F(0, X2, .,Xn) + X1’. F(0, X2, ....,Xn) -,Xn)] - [X1’+ F(1, X2, ....,Xn)] Now consider the Carry—Out from a full—adder. Cout is a function of (X, Y, Cin) Cout=F(Cin,X,Y)=X.Cin +Y.Cin+X.Y=Cin.(X+Y)+X.Y If Cin = 0, then Cout = X. Y and if Cin = 1, then Cout = X + Y Based on the above, produce Cout by completing as many of the four logics as possible. 4/1/05 x:D \ V } Cout ):/ :3“ ) COI1t :Dr 3 y . 3 y . Cm Cm ’ >§ Cout “I __ Cout ); Cin >§ Cin 304 / EElOZL Midterm #l - Spring 2005 l / 8 @ Copyright 2005 Gandhi Puvvada ee102_rnidterml__Sp2005.fm 1.4 A student tried to build two demuxes. He is not sure if any of them are right and if so whether they mach with any/multiple of the symbols on the right. State if there is match and label the 9% inputs and outputs of the circuit(s) which matched. D i / \ f \ D0 —— /D0—- 5 D D S Dl __ S lDlm Do D \ (39/ \ / Matches with symbol A / \ / \ @B/C/D/none) D0 me /D /D 3 D1 S /Dl lb‘ \ (9/ \ an S IDo / D Matches with symbol D (A/B/C/©/none) 1.5 Open—collector wire~ANDing to eliminate logic on the mother board: Mr. Bruin had the following logic on his mother board. He brought A, B, C, and D from 4 add-on cards, produced the result R and returned to each of the four cards. flBruin’s logic on motherboaa\ grams 5 Lima‘QaE eggs} W 2:37 was?”ng 3:3» Qgtgfmfi K 6&3 {33% gifiim 1’55 {avg}? n flim ~ F a3} a. gig: 1‘6.le ’ “5&9; New? t3 é a M “if” a 7 So, Mr. Trojan/Miss Trojan, how do you propose to improve the design to combine the 5 traces ‘E " 5%" 5 i3 ’2’ into one trace on the motherboard and also reduce two ed 6 connection ins into one in on each g P p add-on card? Note: Like in your homework #3 solution (page 5/ 12), you are allowed to use inverters to suit. You would use Open—Collector gates (select one or more) x/ ’9’ \ . g g 3333}; @011 the add—on cards to send Signal to the mother board V (b) on mother board to process the incoming signals and produce result (c) on add—0n cards to receive the result from the mother board and further process it. 4/1/05 EElOZL Midterm #1 ~ Spring 2005 2 / 8 © Copyright 2005 Gandhi Puvvada ee102~midtennl_Sp2005.fin 1.6 4/1/05 Mr. Bruin wanted a decoder with active-high outputs but he could find only a decoder with active-low outputs. He has a bunch of inverters and he is not sure. Help him select one or more choices from among the following. If multiple choices are possible, rank them in the order of your preference. (a) add two inverters at A1, A0 inputs. dd four inverters at the four outputs (0) add inverters at the input as well as outputs ((1) none of these; add g; is". aeeafiéi ‘3 {3g , One student says that the choice (c) above is equivalent to adding no inverters at all. True / i 5;. test figmafiffi m gfigfigfisfié fies: naive? ' se Mr. Bruin is badly looking for a 4 — input AND gate. Vat: (tel x 52m I r2 :3 n 15 16 17 \g 51 a so Y L? w x Y E F W 3i Ml SZID 11 121 it; Y .. 314 wxvz vi Miss Bruin is badly looking for a 4 - input I l l OR gate. C): Their TA has given them each an 8 - to - l mux. They started starring at the mux! Please help them. izé M. E. and Al. conditions: Mr. Bruin labelled the four diverging state transition arrows with conditions C1, CT, C2, and C72— as shown. He insists that his design is right as is, because it follows M.E. and Al. requirements. Miss Bruin thinks that there shall be a relation between Cl and C2 but she is not able to express herself clearly. What do you think? a " ~ A? an; rag... {3x1 :athaT) gt , 4m? p- : a 7 I haftia t’ Hiram WK (:2 grains v is ME. water‘ve SQ WW _ The conditions associated with the converging arrows (converging on to a state) Passage no? (needfiieed not) follow W such as his. a £5 . Q a” A 53.. 2C (M.E. / A.I./ either MB or A.I/both M.E. and Al) ( Se: points) 3 min. ( é pointsfimin. Some random design to test one- hot method skills: Complete the NSL, etc. for the QSZ Flip-Flop. EEiozL Midterm #1 - Spring 2005 3 / 8 © Copyright 2005 Gandhi Puvvada ee102_midterm1_Sp2005.fm 4 ( points) 20 min. Loop Counter incrementation and checking: State Diagram #1 States: I = Initial; DA = Double A; DB Double B; DAB = Double A as well as B; The five diagrams on the side are similar. Pay attention to when I is incremented and when the NSL looks at 1} "£96 £51 gig» ratiwfi 53:43 i611 Gama. $5 For each diagram, answer the following four questions: 1. How many times A gets doubled? 2. How many times B gets doubled? 3. Any state transition arrows that are NEVER taken? 4. What is the value of I when you are in DONE state? s” {223%. State Diagram #1 S raga/ts immafifisa» 2‘ 8 itiwtélg- am 1% t5 stat. a La mamtaam 3 fi 4. 3: :5 2) C: i’Gl‘ig Svaeéfw 2.13:3). {WW . a a as; State Diagram #2 K“ 1. {a 52mm 3‘53ng E 4. 32% {: raiiéfisvat firmltaa) ‘Qg‘fiii State Dlagram #3 s a Q V 1. £3: €353.53: 3gfifif‘ 2 ESQ/:33: 33W§£fig K} . g ‘ A ‘ 9.: gym 3. Raw 3 {kt-gags 6% “‘9 @fwfia lwii: 4. 3:: {3 @mm ggfi‘EIWQ‘gfl'vgm Em ‘”"(' Egg ‘ "‘\ J; 3%? . x @9‘ State Diagram #4 {32% gm.st a}: ATK / 1. ; Mag; t ‘ was - RESET S Q A gdis /\‘ 2- 5% egg amass X 3- Nana. {flaasa as; use/aim grim.) 4 “if 2: 3:” {$52}: gr S . a Q gt, 2 tate D1agram # V ) W 1. a sag awaw 3 time. 2. % gétfiE 3 Elma? k ACK / 3. Nana; [tag wmfiaB CELVCW...) x! 4' :3 % i 3,. {55:3 fivar fitma 2dig%ja 4/1/05 EEIOZL Midterm #1 - Spring 2005 4 / 8 © Copyright 2005 Gandhi Puvvada eel 02_midterm1_Sp2005.fm 5 ( §%%L§%Zi’ig: 93 points) 36min. Serial Voting Machine 5.1 We want to design a serial voting machine Which inspects THREE votes serially. In this design we need to produce TWO inferences, WON and LOST. The states C and ClN have the same meaning as in HW#7 (i.e Counting and continuing to count with one NO vote previously seen.) NC. (No Connection” 74LS163A K @flflwiflg 2 NOTE Q1 MC3 Q; MC2 $1 MC4 NOTE Q0 Q Q0 Synchronous Master Reset (clay Complete the 5—state state diagram. There are only three votes, V0, V1, and V2. It is “qurj (necessary/ unnecessary) to have the RTL statement, COUNT <= COUNT + 1, in the ClN state. Also complete the table on the right side stating the sequence of states (excluding state I) that the machine will go through for each of the combination of the three votes, V0, V1 , and V2. / i Myee votes can be cast in 8 wayS- Vailgax; Combination Won/Lost Sequence V0 V1 V2 of states Yes Yes Yes Won C C Won Yes Yes No Won C i: mites Yes No Yes Won C C: Cm was Yes No No Lost C £3 (312‘s {93? No Yes Yes Won C figs; Swazi: No Yes No Lost C QM gwmgtt‘ No No Yes Lost C Cm Leg”? No No No Lost C figs; L93? A / 4/1/05 Midterm - 5 / 8 © Gandhi Puvvada ee102_midterm1~Sp2005.fm 5.2 Does it matter whether we derived mc2 (standing for max_count of 2, meaning counter is at 2) in any of the following three ways? YES / ® 9 3 Please explain briefly. Bay, ~ ? ‘ Cow?“ {ex 3&3 E, i S va’ifi; 95? Q: Vela: Q G ‘8 Sea ‘ - 3'? IfiQX-Qwixaeygifii “fifteen, Wgeagfsfi €21. "‘7 <2“ “ r gfilér g 17 “x ’ k 5:1“ ” ix A? 3 M i; 5,502,, qewfi} 5 2mm i” t Cifiuaf 2; igeoamgi & W @aiufi” {ERQERQX % Care Magififigfijzfié- Q1 Q1 8: (gm MC2 ——L{>___ MC2 Q1 Mm Buf Q0 In which sequence(s), the conclusion is relatively quickly made? , ,3 @ V0,V1,V2= for i 9;" “‘9' “Gem WV “‘3 “G “‘3; 5.4 For the above 3—vote design, read the waveform given for the first sequence and find the first 3 g} sequence. V0, V1, V2 : NS 2 NC? ,- 355$ ’ If you are not able to figure—out V2 (vote 2) for any reason, state the reason. Or if you are able to mflgure-out V2 (vote 2), tell us how you figured out V2. “Fmngja gee. $332 on? ingfiggfl’é? V32 ; J eewter was ever {a 2% am me. we: 3&3? states 33% mite m" 33% W fine. i As we enter the WON state or the LOST state, does the counter increment? You expect that the A x 5—. W 6;; counter aim rs ingfammai‘ét {in mamas; m C, es: Gm “E” Cem‘iet gee; AK ' (always increments / ometimes increments / never increments). taxmd {lei}; ‘55 {is eiéifiitfiw W51? amév’a sag 2th was {:25 Les"? £323? as, he get amvewam gage; {Beams {a . . . fiaagfig; , Complete the waveform for the remaining portion. Note that the 74LSl63A has a synchronous (not asynchronous) clearlem’i‘essi we?) see wmfiae Ease? , O F“ N m ‘1' V'" N m Vr V) K) F‘ 00 O\ v—t p—a v-I-d v.4 r-4 ‘30 30 3.33 30 3:3 é’o E’s “o’o é’n é’n 30 $0 E?» 331) on 0: q’I 0| “I 0| 0: 0! <3"I or or on 0| 0! M M J4 M .M M .24 M .M M M M M $4 0 U Q Q 0 U U 0 O U U 0 O U C O O O O O O O O O O O O O .2 .1 ._ .t _. .q ... _ __ fl ._ .. .a .q 0 O Q 0 U U U 0 U U U U 0 U CLK 7 RESET START VOTE ;/ STATE iv {a g 91% t V\; ( Dun ) ACK 4/1/05 EEiozL Midterm #1 - Spring 2005 6/ 8 © Copyright 2005 Gandhi Puvvada e6102.midterml_Sp2005.fin 6 4/ 1/05 ( 3+ 5% t... (2 : points) 2.3:; min. Microprogrammed Control Unit design: A 64x32 ROM has 6 (5 / 6 / 32 / 64 / other) address tier 4;};th (input / output) pins and 3?... (5 / 6 / 32/ 64 / other) data afigflé‘ (input / output) pins. It can support a state diagram (or a microprogram) with up to 6 g (5 / 6 / 32/ 64 / other) states (microinstructions). A microprogram counter of £2 (5 / 6 / 32/ 64/ other) bits is employed to address locations in it. Hence (because of the size of the uPC) the v . Q3“ s: x; A“: (condition select field / branch address field / control signal field) shall be é bifi wide. It is g"? nacaafiarg (necessary / not necessary) to use all locations in the ROM in a given application. 3 The following state machine is similar to the one in your homework #6. Here the light stand i2} "touch sensitive" when in OFF state, but "clap sensitive" when in DIM or BRIGHT states. STATE DIAGRAM IS COMPLETE Introduce three "DUMMY OFF STATES" DMOFFl, DaOFF2, and D_OFF3 to facilitate implementation of a microprogrammed control unit for the above. Complete the state transition conditions below for these new 3 states. / EE102L Midterm #1 — Spring 2005 7 / 8 © Copyright 2005 Gandhi Puvvada ee102_midtennl_Sp2005‘fm ea up the bits (contents) of the microprogram memory. Condition select COND— L- Branch ADDR. a. y l t sucw— «Hun—cu... .— an. a. aroma—ow"- («W-«N r. points) 41% min. Data register with data enable and the thegister in HW#6 question #5: We know that, connecting the X_load signal to the clock pin of a data register is a very common misconception. We discussed 3 problems associated with that unthoughtful design. Do you see/encounter all three problems here, or ...? Problem #1: The designer might be forgetting that he should gather data into the destination register at the end of the clock what}e the result is ready. 1226:6le can. as (Kits 52:3 Mam a. nmgquva ' x v ‘ v 0 Raquela 51'in Trams: 'on . Problem #2: X__load can easily have glitches due to the combinational logic in OFL. Here 01/39 X... [.003 Complete the design of the microprogram control unit below. Connect the missing lines and fill- CONTROL OFF DIM DIM_C BRIGHT ’- x minus const Subtractor fly Problem #3: If you need to load on consecutive clocks, this design fails. we. As no“? manual“ ~ Here L1 .- The remaining 4 weeks are Very important for the midterm #2 and also the project. Please do not miss any class. Thanks. Gandhi 4/1/05 EE102L Midterm #1 - Spring 2005 8 / 8 © Copyright 2005 Gandhi Puvvada . i {)3 or MIL—WW3. ...
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ee102_midterm1_Sp2005_sol - ee102_midtennlMSp2005.fm Spring...

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