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Unformatted text preview: EE201L - Introduction to Digital Circuits Experiment # 4 ee201l_detour.fm [Revised: 2/4/08] 1/14 Experiment # 4 Introduction to FPGAs - Detour Signal Lab 1. Synopsis: This lab introduces the use of Field Programmable Gate Arrays (or FPGAs, for short) for proto- typing of digital circuits. Through the design of a simple state machine for controlling the Detour Signal lights, this lab introduces the digilab experimental FPGA board and demonstrate FPGA design flow. The experimental FPGA board houses a Xilinx Spartan-2 FPGA along with vari- ous input and output devices like push buttons, light-emitting diodes and seven segment displays. This lab introduces how each of those input and output devices can be used in EE 201L designs. 2. Description of the Circuit: You all know the detour signal at road repair sites. It normally has four groups of lights - GL (stands for Group Left), G1, G2 and GR - controlled as shown to indicate detour to the right or detour to the left. Assume that we have a L/R switch to choose left or right sig- nal. The state machine looks at this switch only when it is in the Idle state and then per- forms the required (left or right) sequence and comes back to Idle state. In this lab we will implement the 7-state con- troller using D-flip flops in One-hot method. The state machine given below is almost complete. Some obvious state transition conditions have been intentionally left out. Complete the state diagram before proceeding. (Recall that an unconditional state transition can be labelled with 1 as the condition) . Fig 1: Four groups of LEDs in different states Idle State R1 State (G1 is ON) R12 State (G1, G2 are ON) R123 State (G1, G2, GR are ON) Idle State L1 State (G2 is ON) L12 State (G2, G1 are ON) L123 State (G2, G1, GL are ON) GL G1 G2 GR R1 R12 R123 L123 L12 L1 Idle L/R =0 L/R =1 ~Reset Fig 2: State diagram for the Detour Signal design EE201L - Introduction to Digital Circuits Experiment # 4 ee201l_detour.fm [Revised: 2/4/08] 2/14 3. Introduction to the FPGA Board: An FPGA consists of an array of logic blocks connected via programmable interconnect. A typi- cal FPGA contains anywhere from 64 to tens of thousands of logic blocks and an even greater number of flip-flops. Each configurable logic block (CLB) has one or more D-flip flops and some combinational logic such as muxes, etc. Each CLB is capable of performing a reasonably com- plex function such as implementing a full adders. Our objective in this lab is to understand how to use FPGAs and a more discussion on the architecture of FPGAs can be found in Addendum #2. Xilinx TM Inc. (www.xilinx.com) is one of the major FPGA vendors. We will be using the XC2S30 device from Xilinxs Spartan-2 family of FPGAs. It has approximately 30,000 gates organized in configurable logic blocks (or CLBs). The XC2S30 device used in this lab comes in a TQ144 package. (TQ stands for Thin Quad while 144 represents the number of pins in the package) 3.1 FPGA Boards: Digilab D2XL + Digilab DIO1 Board...
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This note was uploaded on 09/12/2009 for the course EE 201L taught by Professor Puvvada during the Spring '08 term at USC.
- Spring '08