Haken ECE 110 Handout 3 - ECE 110 Transparencies Set 3 for...

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L Haken ECE110 transparencies – set 3 page 1 ECE 110 Transparencies Set 3 for Noon Lecture Lippold Haken Sequential Logic Circuits . ............................................................. 2 SR Latches. ..................................................................................... 3 D Flip-Flops. ................................................................................... 6 JK Flip-Flops. ................................................................................. 8 JK Flip-Flops. ................................................................................. 8 Registers. ....................................................................................... 11 Binary Counter. ............................................................................ 12 Analog to Digital Conversion. ..................................................... 17 2-Dimensional Sampling. ............................................................. 27 Digital Coding of Information . ................................................... 33 Error Detection and Correction . ................................................ 34 Data Compression. ....................................................................... 41 Encryption . ................................................................................... 52 Computer Encryption. ................................................................. 57 Long Keys: Random Key Formation. ........................................ 59 Public Key Cryptography . .......................................................... 62 These transparencies include material by Prof. Tim Trick and Prof. Marie-Christine Brunet
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L Haken ECE110 transparencies – set 3 page 2 Sequential Logic Circuits Output state depends on both the present and past input states.
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L Haken ECE110 transparencies – set 3 page 3 SR Latches SR latches can be implemented several ways: Both the above SR implementations have “memory” because Q and Q-bar feed back into the circuits. Their circuit state depends on previous state and current inputs.
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L Haken ECE110 transparencies – set 3 page 4 SR Practice In an SR flip-flop, Q changes as soon as S or R go HIGH.
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L Haken ECE110 transparencies – set 3 page 5 Clock Signals Often it is desirable to synchronize all parts of a circuit using a clock signal. The clock signal is the heartbeat of the circuit. D and JK flip-flops make use of a clock. They can be “edge triggered” or “level triggered”. Duty Cycle What is the Duty Cycle (T ON /T) for each:
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L Haken ECE110 transparencies – set 3 page 6 D Flip-Flops Like SR latches, D flip-flops have a state that is either 0 or 1. But the way you control that state is different:
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L Haken ECE110 transparencies – set 3 page 7 D Flip-flop Practice For the circuit above, complete the timing diagram below. Be precise abot where Y and Z go High or Low.
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L Haken ECE110 transparencies – set 3 page 8 JK Flip-Flops When are JK flip-flops more useful than D flip-flops? JK flip-flop practice: (1) Complete this timing diagram. (2) What is the clock rate?
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L Haken ECE110 transparencies – set 3 page 9 More JK practice: Complete the timing diagram below for the circuit above. Be careful: Y changes only on the positive clock edge, but X and A can change at any time,
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L Haken ECE110 transparencies – set 3 page 10 Quiz LH10 Edge-triggered JK flip-flop After you complete the timing diagram, fill in this table: t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 Q A Q B Q C
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