HW1S-mr parent - EE 166 HW#1 Review NAME Question 1(20PTS...

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Unformatted text preview: EE 166: HW #1 Review NAME: Question 1 (20PTS): Draw a two-dimensional cross section of an P-channel MOSFET showing the following regions. Source (3pts) Drain (3pts) Gate (3pts) Body (2pts) Poly silicon or Al layer (3pts) Gate SiO2 layer (3pts) Where is the inverted channel created (3pts)? 1 EE 166: HW #1 Review NAME: Question 2 (10PTS): Design the logic for a divide by 4 counter. (In other words, design a circuit that divides a clock frequency by 4.) (Do not use JK) DFF D Q CK Q Fin D DFF Q CK Q Fin/2 Fin/4 2 EE 166: HW #1 Review NAME: Question 3 (10PTS): Using a K-MAP, reduce the following function shown in the truth table below to the minimum amount of min/max terms. A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F 0 1 0 1 1 1 0 0 BC A 0 1 00 0 1 01 1 1 11 1 0 10 0 0 F=AB+AC 3 EE 166: HW #1 Review NAME: Question 4 (10PTS): a. Using standard Boolean Logic symbols (AND, OR, INV) draw the schematic of the reduced function from the previous question. A B F A C b. Redraw the schematic using a minimum of NAND and INV logic gates. A B F A C 4 EE 166: HW #1 Review NAME: Question 5 (10pts): Figures 1-4 represent 4 NMOS Capacitors with a Qi or Fixed Oxide Charge of 5x1010q cm-2. Which has a larger VT, Figure 1 or Figure 2? Which has a larger VT Figure 3 or 4? Poly-Si Poly-Si SiO2 SiO2 NA=1016cm-3 NA=1016cm-3 Figure 1 Figure 2 Poly-Si SiO2 NA=1018cm-3 Poly-Si SiO2 NA=1016cm-3 Figure 3 Figure 4 5 EE 166: HW #1 Review NAME: Question 6 (10pts): 6 EE 166: HW #1 Review NAME: Question 7 (10pts): Show the Linear, Saturation regions of the ID, VDS plot of a mosfet show below. Saturation Linear 7 ...
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