Hw2s - CSE 260 Homework 2 1. (10 points) Verify the...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: CSE 260 Homework 2 1. (10 points) Verify the equation AB + A C D + A B D + A B CD = B + A C D using a truth table. ABCD AB'+A'C'D' + A'B'D + A'B'CD'=L B + A C D =R 0000 0 1 0 0 1 1 1 1 0001 0 0 1 0 1 1 0 1 0010 0 0 0 1 1 1 0 1 0011 0 0 1 0 1 1 0 1 0100 0 1 0 0 1 0 1 1 0101 0 0 0 0 0 0 0 0 0110 0 0 0 0 0 0 0 0 0111 0 0 0 0 0 0 0 0 1000 1 0 0 0 1 1 0 1 1001 1 0 0 0 1 1 0 1 1010 1 0 0 0 1 1 0 1 1011 1 0 0 0 1 1 0 1 1100 0 0 0 0 0 0 0 0 1101 0 0 0 0 0 0 0 0 1110 0 0 0 0 0 0 0 0 1111 0 0 0 0 0 0 0 0 -1- 2. (10 points) Draw a logic diagram that implements the expression A(B + A C D ) + A B (D + CD ) directly. Now simplify the expression and draw a logic diagram for a circuit that implements the simplified expression. A B C D A circuit that implements the original expression is shown above. We can simplify the expression as shown below. A(B + A C D ) + A B (D + CD ) =AB + A B (D + C) =B'(A+A'(C+D)) =B'(A+C+D) The circuit for this is A C D B -2- 3. (15 points) The VHDL process shown below is a replacement for the process in the specification of the calculator in section 2 of the notes. Draw a circuit diagram that corresponds to this version of the calculator. You can include a "subtract" block in your diagram to implement the subtraction operation. process (clk) begin if rising_edge(clk) then if clear = '1' then dReg <= x"00"; elsif add = '1' then dReg <= dReg + dIn; elsif load = '1' then dReg <= dIn; elsif sub = '1' then dReg <= dReg - dIn; end if; end if; end process; 8 8 Din Adder x00 1 0 1 0 8 a b 1 1 0 0 D >C Q 8 result Subtract subtract load add clear clk Here, the subtractor does a-b so we wire up Din to b so we get the desired result. -3- ...
View Full Document

Ask a homework question - tutors are online