Hw3s - CSE 260 Homework 3 1(10 points Rewrite the following VHDL module using only ordinary signal assignments(no conditional assignments entity

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CSE 260 – Homework 3 1. (10 points) Rewrite the following VHDL module using only ordinary signal assignments (no conditional assignments). entity foo is port( a,b,c,d: in std_logic; x: out std_logic; y: out std_logic_vector (1 downto 0); end entity foo; architecture arch of foo begin x <= b and c when a = ‘0’ else not c when a>b else a or d; y <= (a & d) when a = ‘1’ else (b & (not c)) when (b=‘0’ and c=‘1’) else ‘1’ & c; end arch; The revised version of the architecture appears below. These assignments were derived by first simplifying the expressions given above. Click here for details. entity foo is port( a,b,c,d: in std_logic; x: out std_logic; y: out std_logic_vector (1 downto 0); end entity foo; architecture arch of foo begin x <= ((not a) and b and c) or (a and (not b) and (not c)) or (a and b); y(1) <= a or b or (not c); y(0) <= (a and d) or ((not a) and b and c); end arch;
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Hw3s - CSE 260 Homework 3 1(10 points Rewrite the following VHDL module using only ordinary signal assignments(no conditional assignments entity

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