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Hw4s - supplied testbench with comments indicating why you...

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CSE 260 – Homework 4 Due September 17, 2008 1) (20 points) Using the original calculator VHDL code as a starting point, modify the code to add a subtract mode. This should operate as follows: a) When load and add are both high, the result should be dReg – dIn. b) When load is high but add is low, dReg = dIn as before. c) When load is low and add is high, dReg = dReg + dIn as before. Make as few changes to the code as possible, but also make it readable and obvious what you are doing. Do not use subtraction, however. This is a 2’s complement calculator so add the negative, do not subtract. The use of a subtraction operator (-) will mean zero credit for this problem. DO NOT USE SUBTRACTION!!!!! Simulate your design using the testbench supplied with this homework (on the website). You may also add whatever additional tests you’d like, but do not turn them in. You are required to turn in a printout of your VHDL code and a printout of your simulation of the
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Unformatted text preview: supplied testbench with comments indicating why you believe the circuit works as you expect. You may draw, by hand, on the printout if that’s easiest. Only the architecture changes, so that’s all I show, here: architecture a1 of calculator is signal dReg: std_logic_vector(15 downto 0); begin process (clk) begin if rising_edge(clk) then if clear = '1' then dReg <= x"0000"; elsif load = '1' then if add = '1' then dReg <= dReg + ((not dIn) + 1); else dReg <= dIn; end if; elsif add = '1' then dReg <= dReg + dIn; end if; end if; end process; result <= dReg; end a1; - 1 - The output from the testbench looks like this once we remember to use 2’s complement. That is, if one adds xFFFF, that’s the same as subtracting one, for example. Clear result x5555+xAAAA = xFFFF x5555+xFFFF = x5554 x5554+x0001= x5555 x5555+x0002= x5557 x5557-x0003= x5554 xFFFF+x0025= x0024 x5554-x5555= xFFFF Load x5555 - 2 -...
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