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Unformatted text preview: supplied testbench with comments indicating why you believe the circuit works as you expect. You may draw, by hand, on the printout if thats easiest. Only the architecture changes, so thats all I show, here: architecture a1 of calculator is signal dReg: std_logic_vector(15 downto 0); begin process (clk) begin if rising_edge(clk) then if clear = '1' then dReg <= x"0000"; elsif load = '1' then if add = '1' then dReg <= dReg + ((not dIn) + 1); else dReg <= dIn; end if; elsif add = '1' then dReg <= dReg + dIn; end if; end if; end process; result <= dReg; end a1; - 1 - The output from the testbench looks like this once we remember to use 2s complement. That is, if one adds xFFFF, thats the same as subtracting one, for example. Clear result x5555+xAAAA = xFFFF x5555+xFFFF = x5554 x5554+x0001= x5555 x5555+x0002= x5557 x5557-x0003= x5554 xFFFF+x0025= x0024 x5554-x5555= xFFFF Load x5555 - 2 -...
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- Spring '09