Hw6s - source code listing for this homework(no simulation output is required entity div2 is port x in std_logic_vector(3 downto 0 result out

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- 1 - CSE 260 Homework 6 Due September 24, 2008 1. (10 points) Write a VHDL module that has a single 4 bit input x and returns a 4 bit value equal to the x /2, in the format of a fixed-point number jkl.m . Implement your circuit using a table of constants. You will need the following function declaration that converts a signal of type std_logic_vector to integer , since the index used in an array must be of type integer . function int(d: std_logic_vector) return integer is -- Convert logic vector to integer. Handy for array indexing. begin return conv_integer(unsigned(d)); end function int; While you may wish to write this and simulate it in the Xilinx tools, you only need to provide your
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Unformatted text preview: source code listing for this homework (no simulation output is required). entity div2 is port ( x: in std_logic_vector(3 downto 0); result: out std_logic_vector(3 downto 0)); end div2; architecture arch of div2 is type table is array(0 to 15) of std_logic_vector(3 downto 0); signal div2Tbl: table := ( "0000", "0001", "0010", "0011", "0100", "0101", "0110", "0111", "1000", "1001", "1010", "1011", "1100", "1101", "1110", "1111", ); function int(d: std_logic_vector) return integer is -- Convert logic vector to integer. Handy for array indexing. begin return conv_integer(unsigned(d)); end function int; begin result <= div2Tbl (int(x)); end arch;...
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This document was uploaded on 09/21/2009.

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