Hw8s - CSE 260 Homework 8 Due October 6, 2008 1. (15...

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- 1 - CSE 260 Homework 8 Due October 6, 2008 1. (15 points) Write a VHDL module that implements a serial +3 circuit. This is a circuit that adds three to an input value x . The data input comes into the circuit one bit at a time with the least significant bit first. The circuit has a single output value called plusThree which should be x+3 . So for example, if the stream of input bits for x is 01011 (with most significant bit first), plusThree is 01110. The circuit should also have a reset input that starts the process over with the plusThree output equal to zero (0) while reset is asserted. Start by writing down the state transition diagram for your circuit. Then write your VHDL based directly on your state transition diagram. Clearly show the reset input as well. The state diagram appears below. Copy +2 Start Reset x / plusThree 10/0 11/0 01/0 00/0 01/1 10/0 11/0 10/0 11/0 00/1 +1 00/0 01/1 10/0 11/0 00/1 01/0
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- 2 - -- plusThree add three to the input serial data -- David M. Zar
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Hw8s - CSE 260 Homework 8 Due October 6, 2008 1. (15...

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