Hw9s - CSE 260 Homework 9 Due October 13, 2008 1. (10...

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- 1 - CSE 260 Homework 9 Due October 13, 2008 1. (10 points) Determine if the following circuit has internal hold time violations. If so, show how to modify the circuit to eliminate them. If not, explain why. Assume that the flip-flop setup time is 2 ns, the hold time is 1 ns, that gate delays range from .3 ns to 1.5 ns (min/max), that the flip-flop propagation delay can range from 1 ns to 4 ns and that the clock skew is 1 ns. First item to notice is that the specification for clock-skew is not important since there is only one flip- flop! So now we see if the shortest path from Q to D is less than 1 ns: There are two gates (.3 ns each) plus the clock-to-Q delay through the flip-flop (1 ns) for a total of 1.6 ns delay. This is more than the hold time (1 ns) so there is no hold time violation. 2. (10 points) For the same circuit in Problem 1, specify when changes in D and R are valid before/after clock and also specify when the output, Z , can change after a rising clock assuming that D and R are stable for a long time after that clock. D must be stable for
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Hw9s - CSE 260 Homework 9 Due October 13, 2008 1. (10...

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