Flip-flop - CD54HC109 CD74HC109 CD54HCT109 CD74HCT109 Data...

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1 Data sheet acquired from Harris Semiconductor SCHS140E Features • Asynchronous Set and Reset • Schmitt Trigger Clock Inputs • Typical f MAX = 54MHz at V CC = 5V, C L = 15pF, T A = 25 o C • Fanout (Over Temperature Range) - Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55 o C to 125 o C • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: N IL = 30%, N IH = 30% of V CC at V CC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, V IL = 0.8V (Max), V IH = 2V (Min) - CMOS Input Compatibility, I l 1 µ A at V OL , V OH Pinout CD54HC109, CD54HCT109 (CERDIP) CD74HC109, CD74HCT109 (PDIP, SOIC) TOP VIEW Description The ’HC109 and ’HCT109 are dual J- K flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP). The flip-flop is set and reset by active-low S and R, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition. 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 1R 1J 1K 1CP 1S 1Q GND 1Q V CC 2J 2K 2CP 2S 2Q 2Q 2R Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE CD54HC109F3A -55 to 125 16 Ld CERDIP CD54HCT109F3A -55 to 125 16 Ld CERDIP CD74HC109E -55 to 125 16 Ld PDIP CD74HC109M -55 to 125 16 Ld SOIC CD74HC109MT -55 to 125 16 Ld SOIC CD74HC109M96 -55 to 125 16 Ld SOIC CD74HCT109E -55 to 125 16 Ld PDIP CD74HCT109M -55 to 125 16 Ld SOIC CD74HCT109MT -55 to 125 16 Ld SOIC CD74HCT109M96 -55 to 125 16 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. March 1998 - Revised October 2003 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Dual J- K Flip-Flop with Set and Reset Positive-Edge Trigger [ /Title (CD74H C109, CD74H CT109) /Subject (Dual J- K Flip- Flop with Set and Reset
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2 Functional Diagram Logic Diagram TRUTH TABLE INPUTS OUTPUTS S RC PJ KQ Q LHXXXHL H L XXXLH L L X X X H (Note 1) H (Note 1) H H LLLH H H H L Toggle HH L H No Change HHHL H H L X X No Change H= High Level (Steady State) L= Low Level (Steady State) X= Don’t Care = Low-to-High Transition NOTE: 1. Unpredictable and unstable condition if both S and R go high simultaneously 1S 2S 2 R 5 11 6 7 1 Q 1Q 15 1 1R 2K 13 12 10 9 2 Q 2Q 2CP F/F 1 F/F 2 GND = 8 V CC = 16 2J 14 1K 3 4 1CP 1J 2 S J K CL CL R Q Q 6(10) 7(9) Q Q 5(11) S 2(14) J 3(13) K 4(12) CP 1(15) R FF V CC GND 16 8 CD54HC109, CD74HC109, CD54HCT109, CD74HCT109
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3 Absolute Maximum Ratings Thermal Information DC Supply Voltage, V CC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, I IK For V I < -0.5V or V I > V CC + 0.5V . . . . . . . . . . . . . . . . . . . . . .± 20mA DC Drain Current, per Output, I O For -0.5V < V O < V CC + 0.5V . . . . . . . . . . . . . . . . . . . . . . . . . .± 25mA DC Output Diode Current, I OK For V O < -0.5V or V O > V CC + 0.5V . . . . . . . . . . . . . . . . . . . .± 20mA DC Output Source or Sink Current per Output Pin, I O For V O > -0.5V or V O < V CC + 0.5V . . . . . . . . . . . . . . . . . . . .± 25mA DC V CC or Ground Current, I CC . . . . . . . . . . . . . . . . . . . . . . . . .± 50mA
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This note was uploaded on 09/22/2009 for the course MECH EN.530.101 taught by Professor Okamura during the Spring '09 term at Johns Hopkins.

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Flip-flop - CD54HC109 CD74HC109 CD54HCT109 CD74HCT109 Data...

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