lec2 - CS575ParallelProcessing...

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CS575 Parallel Processing  Lecture two:Parallel Computer Models Wim Bohm Colorado State University Except as otherwise noted, the content of this presentation is licensed under  the Creative Commons Attribution 2.5 license
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CS575 lecture 2 2 Instruction and Data Streams  John von Neumann Stored program architecture One instruction stream, One data stream Michael Flynn:  Taxonomy of //computers SISD: sequential    SIMD: data parallel MIMD:multi processing
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CS575 lecture 2 3 SISD Limiting factors Instruction execution rate Memory bandwidth ~100* slower than instruction rate Increasing Memory Bandwidth: Caches (level 1, level 2) Prefetch Memory interleaving
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CS575 lecture 2 4 How did instruction rate get so high?   Higher clock rates Instruction Level Parallelism (ILP) ‘RISC’ architectures Pipelining Multiple functional units Reservation stations Speculation / branch prediction
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CS575 lecture 2 5 SIMD One control unit Many processing elements All executing the same instruction Local memories Conditional execution Where ocean perform ocean step Where land perform land step Gives rise to idle processors PE interconnection Usually a 2D mesh
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CS575 lecture 2 6 SIMD machines Bit level  ILLIAC IV (very early research machine, Illinois) MPP (Burroughs) DAP (ICL) CM2 (Thinking Machines)
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This note was uploaded on 09/24/2009 for the course CS 525 taught by Professor Rjyosy during the Winter '09 term at Central Mich..

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lec2 - CS575ParallelProcessing...

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