Theoretically supposed to exploit alll parallelism

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Unformatted text preview: Theoretically supposed to exploit alll parallelism available in the problems. In practice many times it does no better than Pipeline architectures 3. Systolic Architectures: Special purpose Systolic fine grain architectures . 4. Neural Architectures 4. s ASYNCHRONOUS MULTIPROCESSORS ASYNCHRONOUS Coarse Grain Architectures M Common Bus MEMORY Processor Memory Switch M .. M CPU CPU… CPU CPU CPU . . CPU Shared Memory Multiprocessors Switch Based CPU MEM CPU MEM CPU MEM Connection Network Message Based Multiprocessor ASYNCHRONOUS MULTIPROCESSOR ASYNCHRONOUS CPU MEM MEM CPU CPU MEM Connection Network MEM MEM MEM Hybrid Approach(Shared Memory and Message Based Multiprocessor Coarse Grain Multiprocessor General Purpose SYNCHRONOUS MULTIPROCESSORS Fine grain parallel Processor CU + Scaler Processor PE + MEM + MEM PE PE + MEM Interconnection Network PE : Processing Element MEM : Memory CU : Control Unit Employs Message Based Communication Parallelism at basic operation level and used widel...
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This note was uploaded on 09/24/2009 for the course CS 525 taught by Professor Rjyosy during the Winter '09 term at Central Mich..

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