Unformatted text preview: y in Vector processors. PIPELINE PROCESSORS PIPELINE
Idea: Assembly Line FETCH INST DECODE DATA FETCH EXEC Instruction Processing Pipieline
Fine Grain Genral Purpose Architecture Systolic Architectures
MEMORY MEMORY f1 f2 .. f n f1 f2 .. fn Conventional Systolic Special Purpose Fine Grain Architectures NEURAL ARCHITECTURES NEURAL
s X1 x2 W1 W2 Th y Wn Xn y = f(
INPUT w i . Xi - Th ) Network of Neurons constitutes a computer OUTPUT DATA FLOW ARCHITECTURES DATA x1 x2 x3 2 + 10 + 5 * y = (x1+x2) * (x2+x3) n n Tokens are data values Each node is an operator with input lines as shown the operator fires and produces the output value which is placed as token on the output arcs of the operator Execution process thus becomes data driven n When input lines have data(Token shown as dot) Architectures built on this principle are called (data flow architectures) CLASSIFICATION SCHEMES CLASSIFICATION
s FLYNN’S CLASSIFICATION BASIS 1. Streams of instructions and data Streams Programs execu...
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This note was uploaded on 09/24/2009 for the course CS 525 taught by Professor Rjyosy during the Winter '09 term at Central Mich..
- Winter '09