Chapter1 - Digital Integrated Circuits Prof. Saeed...

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- 0 - Digital Integrated Circuits Prof. Saeed Mohammadi Purdue University
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- 1 - Chapter 1. Review: Digital CMOS Technology In this chapter, we review the basics of digital CMOS design. We introduce the CMOS inverter and discuss noise and timing issues that a designer should consider when designing a digital circuit. Logic design (concept of 0s and 1s) is a very familiar topic. A digital microprocessor can perform logic functions (and arithmetic function as well) using digital gates. Digital gates are built using transistors. Since late 1980’s complementary metal oxide semiconductor (CMOS) technology has been the technology choice for implementing digital circuit and almost 99.99% of digital circuits nowadays are fabricated in CMOS technology. There are several reasons for that. The main two reasons are low cost and zero static power dissipation of this technology. CMOS transistors are basically the building blocks of digital gates. In this course we learn how to design digital and logic circuits using CMOS transistors. Let use start with the concept of logic levels. In binary logic, we have two levels, level 0 and level 1. They usually correspond to a voltage level (or sometimes current value in a branch). In CMOS, 0 and 1 correspond to Gnd (and voltage close to 0V) and V DD , the voltage at the power supply. Assume V DD =1.8V. Then 0 0.2 V 1 1.8 V The first issue is to make sure thatwe don’t interpret the data wrong. 0 V b reads logic 0 0.7 V b logic 0 or logic 1 ? Obviously 0.7V is not a defined logic here and should be avoided. The second issue here is what causes a logic gate to have 0.7 V at its terminal? The answer could be summarized in one word: Noise Noise in Digital Integrated Circuits noise undesired coupling In digital circuit noise is referred to any undesired signal or undesired signal coupling that cause the logic level to stray away from 0 and 1 levels. Although ideally all the signal couplings can be
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- 2 - calculated or simulated, in practice one cannot calculate the overall coupling due to large size of
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This note was uploaded on 09/24/2009 for the course ECE 456 taught by Professor Mohammadi during the Spring '09 term at Purdue University-West Lafayette.

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Chapter1 - Digital Integrated Circuits Prof. Saeed...

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