Chapter2 - - 11 - Chapter 2. CMOS Technology and Device...

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Unformatted text preview: - 11 - Chapter 2. CMOS Technology and Device Physics Outcomes of scaling (shrinking the features sizes of CMOS transistor) Smaller feature size : Density ↑ Switching speed ↑ → for the same switching speed: dynamic power ↓ V DD ↓ → power dissipation decreases Leakage ↑ → static power ↑ Cost/cm 2 ↓ However, cost per critical mask ↑ 0.13 μ $1M/step cost/transistor ↑ Complexity ↑ CMOS Process Modern processes use epi-layer - 12 - IBM → 65nm transistors on SOI substrate → f T , f max > 250GHz Silk layer (Dow chemical ) 8-level of metallization → 2 of them are Cu (Copper interconnect ) 0.6V supply (digital) 0.9V supply (analog) When you do scaling below 0.25μm technology (0.25μm is the minimum distance between source and drain contacts), your transistor operates under short channel effects Short channel effects Technology Review Si-wafer Thickness Resistivity Size 2mm(MEMS App.) P- lightly doped sub. (30-100 Ω cm) 4” 1mm P+ highly doped (1-10 Ω cm) ↓ 400 μ high resistivity ( 10k Ω cm) 12” after processing 1k Ω cm 200 μ , 100 μ , 50 μ difficult to handle - 13 - Bulk → Bulk CMOS SOI → partially depleted, fully depleted reduced parasitics → better performance 20% ↑ better on-off characteristics Simox wafers → implanting Oxygen in Si wafer Photolithography used for selective masking Diffusion and Ion Implantation Diffusion - 14 - Ion Implantation : Dose, and Energy of ions determine the profile of doping Deposition Field oxide, Si 3 N 4 sacrificial (mask for ion implantation) Etching Wet & Dry etching (RIE-Reactive Ion Etching) Planarization For easy masking process and obtaining high yield - 15 - Select layers - 16 - CMOS Process Design rule (0.25 μ ) → set of minimum dimensions and spacing to get ~100% yield ⇒ to form a transistor DRC (Design Rule Check) uses a technology file LVS (Layout vs. Schematic) Extract circuit from layout → calculate parasitics - 17 - IC Packaging Package account for 50% of delay Different Packages : DIP → Dual-In-Line package PGA → Pin-Grid-Array . . Surface mount → remove package → testing is difficult Thermal Consideration p G t N ≤ E Δ T θ N G : number of gate/IC , t P : Propagation delay ∆ T : max Temp. difference between IC & Environment θ : thermal resistance from chip to environment E : switching energy of each gate ∆ T/ θ = Q : total power of IC Q ⋅ t p = PDP : Power Delay Product NG ⋅ E = total dynamic energy → assuming all gate are opening simultaneously so thermal properties determine maximum integration level → activity factor = active gates/ total gates - 18 - Devices • Semiconductor Physics review • Diode • MOS transistor Semiconductor Physics Charge carriers in semiconductors : electrons, holes Why do we consider holes?...
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This note was uploaded on 09/24/2009 for the course ECE 456 taught by Professor Mohammadi during the Spring '09 term at Purdue University.

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Chapter2 - - 11 - Chapter 2. CMOS Technology and Device...

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