Chapter3

Chapter3 - Chapter 3. Interconnects Interconnects Assume 3...

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36 Chapter 3. Interconnects Interconnects Assume 3 lines: divide them into equal sections b high resistance small capacitance high inductance b high impedance line (inductive) b high capacitance small resistance small inductance b low impedance line (capacitive) When you apply a signal (sharp step function) b Capacitive lines are suitable for power distribution b They kill the signal. delay due to finite length delay due to RLC charging b more suitable for signal provided the resistance is low
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37 Line capacitance C = ε di di t WL d A ε = b first order approximation As you go to deep submicron, make W , but to reduce resistance you make H Submicron interconnect C wire = C pp + C fringe = ) / log( 27 2 / H t t H W di di di + - : be careful using this formula Parallel plate capacitance L W H t di Oxide H W fringe field W H t di field fringe field C due to fringe field 1 W/t di or W/H 1pF/cm
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Interwire capacitance Table 4.2 (page 143 of your text book) gives average capacitance between PP (parallel plate) and fringe. Different interconnects in 0.25 μ process Poly – field oxide b high capacitance Metal – active > metal – field oxide Table 4.3(page 144 of your text book) gives interwire capacitance on same level. Resistance HW L R ρ = ρ : resistivity ( Ω cm) , H : constant W L R R = R : sheet resistance(( Ω /sq) Silicide and polycide are used to reduce sheet resistance of diffusion/poly layers. n + , p + n + , p + + silicide Poly Polycide Al R 50 ~ 150 3 ~ 5 150 ~ 200 4 ~ 5 0.05 ~ 0.1 Unlike metal Si 2 W and Si 2 Ti can stand high temperature processing. Metal
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This note was uploaded on 09/24/2009 for the course ECE 456 taught by Professor Mohammadi during the Spring '09 term at Purdue.

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Chapter3 - Chapter 3. Interconnects Interconnects Assume 3...

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