Midterm2Question3 - Question7 Explain in details how...

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Examples of Question Number 3 of Midterm 2 EE456 Question1: Draw transistor level implementation of a static negative edge-triggered flip-flop. Use transmission gate logic for multiplexer implementation. Question2: Draw transistor level implementation of a dynamic negative edge-triggered flip-flop using (a) transmission gates (b) NMOS only. Estimate the 3 important delay times (t su , t hold and t c-q ) in NMOS design only. Assume the inverter and transmission gate delays are known (t inv and t tx ). Question3: Draw gate level implementation of a non-overlapping clock generator and explain how it works and why the outputs are non-overlapping. Question4: Draw transistor level implementation of a C 2 MOS master-slave flip-flop and show that it is insensitive to 00 and 11 overlapping clocks. Question5: Draw transistor level implementation of a true single phase register combined with a 3-in NOR gate as the input data. Question6: Explain with an example how pipelining can speed-up a sequential function.
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Unformatted text preview: Question7: Explain in details how pre-diffused and pre-wired arrays operate. Question8: Explain how fuse and antifuse are realized in an FPGA. What are the advantages and disadvantages of fuse and antifuse. Question9: What are the design techniques to reduce cross-talk in a dense digital integrated circuit. Question10: By defining delay factor (g), show how the delay of a bus line is dependent on the input signals on that line and also on the next adjacent lines. Question11: Explain how wide transistors for output pad buffers are implemented. Question12: What is a tri-state buffer. Show two different implementation of a tri-state buffer and explain how they work. Question13: Why reduced voltage swing helps reducing the gate delay time. Draw an implementation of driver/receiver network implemented using static reduced swing voltage technique and explain how it works....
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