Midterm2Solutions - D EE456 Midterm 2 April 14'11.09 Name:...

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Unformatted text preview: D EE456 Midterm 2 April 14'11.09 Name: Exam time: 75 minutes Answer all 3 questions. You will loose points if your answers are not legible. Problem 1 (3 points) Draw transistor level implementation of a dynamic negative edge-triggered register using (a) transmission gates (b) NMOS pass transistor logic. Explain how they operate. Estimate the three important delay times (t su , thold and t c- q ) in transmission gate logic design only. Assume the inverter and transmission gate delays are known (tinv and ttx). Your answer will be graded based on both your descriptions and fonnulas you write. Therefore provide ample explanations. loJ-<.J, ~--. 6i tA ----. -t 1I.e - V~ lakL1 D '-- J I\.- .. ~-J b",-c;VV\S"~'SS i6"YI J:c "DO D lrr-0VVl q I') 6v Q(J(); ( (A.,wr~ h.h~ Cb) NMOS Fa c;S :v..vu. kh Noh. , Yfh'\. P-h 1\ Y\-U..d PMOS 'fm- \'D}) -'~ "'Ill) t~~ elk ~C2 ...J L--I/-t I ",J.ch-t ~~ l", kl.t EE.+56 Midterm :2 April l.+ th 09 Name: Exam time: 75 minutes M-G\.J 1 """tkL f-~~t trewtSK.HS5i4Vl jetk - ttx y ~ d. b-eo f7Y1 cl. t1u.. _I/fl --e.~ ~ tfu dock. ~ wvor'( ~ t-o rvJ-o.p f/) _ ~ "* 2 EE-I56...
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This note was uploaded on 09/24/2009 for the course ECE 456 taught by Professor Mohammadi during the Spring '09 term at Purdue University-West Lafayette.

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Midterm2Solutions - D EE456 Midterm 2 April 14'11.09 Name:...

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